Controlling instruction alternative selection

I'm working with a CPU having a restricted set of registers that can do three address maths wheres ALL registers can do two address maths. If I define (define_insn "addsi3" [ (set (match_operand:SI 0 "register_operand" "=r,r") (plus:SI (match_operand:SI 1 "register_o

Re: match_scratch causing pattern mismatch

Of course, the answer is to emit_insn( gen_comparesi3( op0, op1 )); which generates the required match_scratch instead of ... cmpmode = SELECT_CC_MODE( branchCode, op0, op1 ); flags = gen_rtx_REG ( cmpmode, CC_REGNUM ); compare = gen_rtx_COMPARE ( cmpmode, op0, op1 ); emit_ins

match_scratch causing pattern mismatch

in a GCC port to a 16 bit cpu that uses CC flags for branching, I'm experimenting with using a 32 bit subtract for compare instead of multiple 16 bit compares and branches. my cbranch4 expander produces a compare and conditional branch patterns... cmpmode = SELECT_CC_MODE( branchCode, op0,

Function attribute((optimize(...))) ignored on inline functions?

I'd like to tell gcc that it's okay to inline functions (such as rintf(), to get the SSE4.1 roundss instruction) at particular call sights without compiling the entire source file or calling function with different CFLAGS. I attempted this by making inline wrapper functions annotated with attribut