Re: GCC/JIT and precise garbage collection support?

2015-07-09 Thread David Malcolm
On Fri, 2015-07-10 at 00:17 +0200, Basile Starynkevitch wrote: > Hello All, > > (this is triggered by a question on the Ocaml mailing list asking about > SystemZ backend in Ocaml; SystemZ is today a backend for GCC & probably > GCCJIT) > > We might want to support better good garbage collection

Re: Allocation of hotness of data structure with respect to the top of stack.

2015-07-09 Thread Vladimir Makarov
On 2015-07-05 7:11 AM, Ajit Kumar Agarwal wrote: All: I am wondering allocation of hot data structure closer to the top of the stack increases the performance of the application. The data structure are identified as hot and cold data structure and all the data structures are sorted in decrea

Re: [RFC] Design and Implementation for Path Splitting for Loop with Conditional IF-THEN-ELSE

2015-07-09 Thread Jeff Law
On 06/02/2015 10:43 PM, Ajit Kumar Agarwal wrote: -Original Message- From: Jeff Law [mailto:l...@redhat.com] Sent: Tuesday, June 02, 2015 9:19 PM To: Ajit Kumar Agarwal; Richard Biener; gcc@gcc.gnu.org Cc: Vinod Kathail; Shail Aditya Gupta; Vidhumouli Hunsigida; Nagaraju Mekala Subject:

GCC/JIT and precise garbage collection support?

2015-07-09 Thread Basile Starynkevitch
Hello All, (this is triggered by a question on the Ocaml mailing list asking about SystemZ backend in Ocaml; SystemZ is today a backend for GCC & probably GCCJIT) We might want to support better good garbage collection schemes in GCC, particularily in GCCJIT. This is a thing that LLVM is kno

Understanding uses of a statement and def-use chains

2015-07-09 Thread rohit bhatia
Hi I am implementing a GCC Pass as IPA_Pass before the pass "whole-program". I am using LTO to run my pass once during linking phase. I am having trouble interpreting the results of the def-use chains for SSA Variables. I am traversing the def use chains backwards to access the variables that aff

Proposal to postpone release of 5.2 for a week [Was: Re: patch to fix PR66782]

2015-07-09 Thread Uros Bizjak
Hello! > The patch was bootstrapped and tested on x86/x86-64. > > Committed as rev. 225618. > > 2015-07-09 Vladimir Makarov > > PR rtl-optimization/66782 > * lra-int.h (struct lra_insn_recog_data): Add comment about > clobbered hard regs for arg_hard_regs. > * lr

Re: Question about DRAP register and reserving hard registers

2015-07-09 Thread H.J. Lu
On Thu, Jul 9, 2015 at 9:31 AM, Steve Ellcey wrote: > On Mon, 2015-06-29 at 11:10 +0100, Richard Henderson wrote: > >> > OK, I think I have this part of the code working on MIPS but >> > crtl->drap_reg is used in the epilogue as well as the prologue even if >> > it is not 'live' in between. If I

Re: Question about DRAP register and reserving hard registers

2015-07-09 Thread Steve Ellcey
On Mon, 2015-06-29 at 11:10 +0100, Richard Henderson wrote: > > OK, I think I have this part of the code working on MIPS but > > crtl->drap_reg is used in the epilogue as well as the prologue even if > > it is not 'live' in between. If I understand the code correctly the x86 > > prologue pushes t

Testing and dynamic linking on remote target

2015-07-09 Thread David Talmage
I'm looking for a way to specify the LD_LIBRARY_PATH or LD_PRELOAD on the target system when running one of the DejaGNU test suites. I'm testing a gcc cross-compiler on a development board. I can't replace existing versions of libraries under test because other people are using the development

Re: %fs and %gs segments on x86/x86-64

2015-07-09 Thread Armin Rigo
Hi all, Here is an updated patch (attached) for __seg_fs and __seg_gs: * added a target hook "default_pointer_address_modes" to avoid disabling a few gcc optimizations which, according to my reading of the documentation, should continue to work even in the presence of multiple address spaces as l

Re: [AArch64] Missed vectorization opportunity in cactusADM

2015-07-09 Thread Ramana Radhakrishnan
>> yes, that '50' should be a parameter somewhere in loop_vec_info. > > I see the broken code is still in aarch64.c - can someone please test > & apply the above > patch? I believe this is on Alan's todo list. Ramana > > Thanks, > Richard. > >> Richard. >> >>> Thanks, >>> James >>> >>> --- >>> [

Re: [AArch64] Missed vectorization opportunity in cactusADM

2015-07-09 Thread Richard Biener
On Thu, Apr 9, 2015 at 9:52 AM, Richard Biener wrote: > On Wed, Apr 8, 2015 at 5:14 PM, James Greenhalgh > wrote: >> On Thu, Apr 02, 2015 at 04:20:06AM +0100, Ekanathan, Saravanan wrote: >>> (I had sent this mail to gcc-help a week ago. Not sure, all GCC developers >>> are subscribed to gcc-help,

Re: making the new if-converter not mangle IR that is already vectorizer-friendly

2015-07-09 Thread Richard Biener
On Fri, Jul 3, 2015 at 11:37 AM, Alan Lawrence wrote: > Abe wrote: > >> In other words, the problem about which I was concerned is not going to be >> triggered by e.g. "if (c) x = ..." >> which lacks an attached "else x = ..." in a multithreaded program without >> enough locking just because 'x'

Re: making the new if-converter not mangle IR that is already vectorizer-friendly

2015-07-09 Thread Richard Biener
On Tue, Jul 7, 2015 at 10:55 PM, Abe wrote: > [Alan wrote:] > >> My understanding is that any decision as to whether one or both of y or z >> is evaluated (when 'evaluation' involves doing any work, >> e.g. a load), has already been encoded into the gimple/tree IR. Thus, if >> we are to only evalu

Re: CFG transformation of loops with continue statement inside the loops.

2015-07-09 Thread Richard Biener
On Wed, Jul 8, 2015 at 4:46 PM, Ajit Kumar Agarwal wrote: > All: > > While/For ( condition1) > { >Some code here. > If(condition2 ) > continue; > Some code here. > } > > Fig(1) > > For the above loop in Fig(1) there will be two backedges and multiple > latches. The below code can be