On 10.01.15 01:00, Joel Sherrill wrote:
FWIW fixing the semicolon only let's the build get to an ICE. :(
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64551
Applied the proposal and was able to build a cross-compiler.
Andreas
On January 9, 2015 4:00:38 PM CST, Jan-Benedict Glaw
wrote:
On January 9, 2015 4:00:38 PM CST, Jan-Benedict Glaw wrote:
>On Fri, 2015-01-09 15:05:52 -0600, Joel Sherrill
> wrote:
>> Hi
>>
>> Does anyone else see this? There is a semi-colon at the end of
>> gcc/config/arm/arm.h:771 which I don't think should be there.
>>
>> g++ -c -g -O2 -DIN_GCC -DC
On Fri, 2015-01-09 15:05:52 -0600, Joel Sherrill
wrote:
> Hi
>
> Does anyone else see this? There is a semi-colon at the end of
> gcc/config/arm/arm.h:771 which I don't think should be there.
>
> g++ -c -g -O2 -DIN_GCC -DCROSS_DIRECTORY_STRUCTURE -fno-exceptions
> -fno-rtti -fasynchronous-u
Appologies,
this is mine. But I couldn't bootstrap arm so far.
On 09.01.15 22:05, Joel Sherrill wrote:
Does anyone else see this? There is a semi-colon at the end of
gcc/config/arm/arm.h:771 which I don't think should be there.
g++ -c -g -O2 -DIN_GCC -DCROSS_DIRECTORY_STRUCTURE -fno-exce
Hi
Does anyone else see this? There is a semi-colon at the end of
gcc/config/arm/arm.h:771 which I don't think should be there.
g++ -c -g -O2 -DIN_GCC -DCROSS_DIRECTORY_STRUCTURE -fno-exceptions
-fno-rtti -fasynchronous-unwind-tables -W -Wall -Wno-narrowing
-Wwrite-strings -Wcast-qual -Wmissi
On 01/09/15 08:32, Joel Sherrill wrote:
Piling on here. For RTEMS, we have 5 targets with GCC PRs reported.
Ignoring the avr and m32c, we have arm, m68k and nios2 all with
regressions since 4.9. I think these PRs are important enough
that they should get consideration:
+ arm: ICE GCC PR64460 se
On Fri, Jan 9, 2015 at 6:37 AM, Andrew Haley wrote:
> On 01/09/2015 12:30 PM, Richard Biener wrote:
>> Does --disable-lto-plugin work?
>
> Over to you, Cyd.
>
> Andrew.
>
Yes, it allows the build to continue successfully. Specifically it
allows the libgcc_s.so to be built.
Brief background: the
Piling on here. For RTEMS, we have 5 targets with GCC PRs reported.
Ignoring the avr and m32c, we have arm, m68k and nios2 all with
regressions since 4.9. I think these PRs are important enough
that they should get consideration:
+ arm: ICE GCC PR64460 segfault for -O2 and xscale
+ m68k: GCC PR64
I noticed that there are three symbols in libgcc with no leading __:
isinfd32, isinfd64, isinfd128. Is there any reason for that? As far
as I can see GCC will never generate calls to those functions
(especially because PR 43374 means that the isinf macro doesn't
currently work for decimal floatin
On 01/09/2015 12:30 PM, Richard Biener wrote:
> Does --disable-lto-plugin work?
Over to you, Cyd.
Andrew.
On Fri, Jan 9, 2015 at 1:16 PM, Andrew Haley wrote:
> On 01/09/2015 10:33 AM, Richard Biener wrote:
>> On Thu, Jan 8, 2015 at 11:12 AM, Andrew Haley wrote:
>>> Android native GCC can't support LTO because of a lack of support for
>>> dlopen() in the C library. How should we patch the configury t
On 01/09/2015 10:33 AM, Richard Biener wrote:
> On Thu, Jan 8, 2015 at 11:12 AM, Andrew Haley wrote:
>> Android native GCC can't support LTO because of a lack of support for
>> dlopen() in the C library. How should we patch the configury to disable
>> LTO by default?
>
> How does LTO need dlope
Hi Ramana,
any chance to get the attribute target support for ARM review in time
for stage 4 ?
Many thanks
Christian
On 01/08/2015 11:32 AM, Jakub Jelinek wrote:
The trunk is still in Stage 3 now, which means it is open for general
bugfixing, but will enter Stage 4 on Friday, 16th, end of d
On Thu, Jan 8, 2015 at 11:12 AM, Andrew Haley wrote:
> Android native GCC can't support LTO because of a lack of support for
> dlopen() in the C library. How should we patch the configury to disable
> LTO by default?
How does LTO need dlopen? It seems it only cannot use the linker plugin
in whi
On Mon, Jan 5, 2015 at 3:27 AM, Ajit Kumar Agarwal
wrote:
>
> The following fig (1) shows an implementation of the SSQ kernel from the BLAS
> Library in ATLAS.
> Fig(2) shows the conversions of the IF-THEN-ELSE in Fig(1) to vectorized
> code. Normally in the automatic vectorization the IF-THEN-E
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