On 9/11/2013, at 12:08 am, Fredrik Olsson wrote:
> I have this simple functions:
> int sum_vec(int c, ...) {
>va_list argptr;
>va_start(argptr, c);
>int sum = 0;
>while (c--) {
>int x = va_arg(argptr, int);
>sum += x;
>}
>va_end(argptr);
>return sum;
>
On 8/11/2013, at 1:48 am, Paulo Matos wrote:
> Hello,
>
> I am slightly unsure if the confusion is in the dependencies or it's my
> confusion.
>
> I have tracked this strange behaviour which only occurs when we need to flush
> pending instructions due to the pending list becoming too large (g
On Wed, Dec 04, 2013 at 03:57:43PM -0500, Jason Merrill wrote:
> On 12/04/2013 03:21 PM, Oleg Endo wrote:
> >Some days ago I've tried building an SH cross-GCC on OSX 10.9 with the
> >latest XCode (clang) tools and its libc++ std lib. Some of the libc++
> >headers use malloc, realloc etc, which are
On 12/04/2013 03:21 PM, Oleg Endo wrote:
Some days ago I've tried building an SH cross-GCC on OSX 10.9 with the
latest XCode (clang) tools and its libc++ std lib. Some of the libc++
headers use malloc, realloc etc, which are poisoned in system.h.
Well, presumably we are poisoning them because
Hello,
Earlier this the following was committed:
2013-06-20 Oleg Endo
Jason Merrill
* system.h: Include as well as .
... so that things like could be included after including
system.h.
Some days ago I've tried building an SH cross-GCC on OSX 10.9 with the
latest XCode
On 12/03/2013 09:22 AM, Philip Herron wrote:
Hey all
Some of you may have noticed the gccrs branch on the git mirror. Since
PyCon IE 2013 i gave a talk on my Python Front-end pet project and
heard about rust by a few people and i never really looked at it
before until then but i've kind of be
On 12/4/2013, 6:15 AM, Tejas Belagod wrote:
Hi,
I'm trying to relax CANNOT_CHANGE_MODE_CLASS for aarch64 to allow all
mode changes on FP_REGS as aarch64 does not have register-packing, but
I'm running into an LRA ICE. A test case generates an RTL subreg of the
following form
(set (reg:
Hi Jakub,
Apologies for the late response.
On Fri, Oct 11, 2013 at 04:05:24PM +0100, Jakub Jelinek wrote:
> On Fri, Oct 11, 2013 at 03:54:08PM +0100, Vidya Praveen wrote:
> > Here's a compilable example:
> >
> > void
> > foo (int *__restrict__ a,
> > int *__restrict__ b,
> > int *__re
On 12/04/13 03:22, BELBACHIR Selim wrote:
Hi,
My target has :
- 2 registers class to store SImode (like m68k, data $D & address $A).
- moves from wide offset MEM to $D or $A (ex: mov d($A1+50),$A2 ormov
d($A1+50),$D1)
- conditional moves from offset MEM to $D or $A but with a restrictio
Hi Richi,
Apologies for the late response. I was on vacation.
On Mon, Oct 14, 2013 at 09:04:58AM +0100, Richard Biener wrote:
> On Fri, 11 Oct 2013, Vidya Praveen wrote:
>
> > On Tue, Oct 01, 2013 at 09:26:25AM +0100, Richard Biener wrote:
> > > On Mon, 30 Sep 2013, Vidya Praveen wrote:
> > >
>
Eric Botcazou writes:
>> Combine is asking simplify-rtx.c to truncate an addition to QImode
>> and simplify-rtx.c is providing a reasonable representation of that.
>> It's the representation we should use when matching against .md patterns,
>> for example. The problem is that combine doesn't want
Hi,
I'm trying to relax CANNOT_CHANGE_MODE_CLASS for aarch64 to allow all mode
changes on FP_REGS as aarch64 does not have register-packing, but I'm running
into an LRA ICE. A test case generates an RTL subreg of the following form
(set (reg:DF 97) (subreg:DF (reg:V2DF 95) 8))
LRA ha
Hi,
My target has :
- 2 registers class to store SImode (like m68k, data $D & address $A).
- moves from wide offset MEM to $D or $A (ex: mov d($A1+50),$A2 ormov
d($A1+50),$D1)
- conditional moves from offset MEM to $D or $A but with a restriction :
offset MEM conditionally move
> Combine is asking simplify-rtx.c to truncate an addition to QImode
> and simplify-rtx.c is providing a reasonable representation of that.
> It's the representation we should use when matching against .md patterns,
> for example. The problem is that combine doesn't want to keep the
> truncation i
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