On 10/22/2012 06:03 PM, David Edelsohn wrote:
> On Mon, Oct 22, 2012 at 9:49 AM, Perry Smith wrote:
>> In stage 3, libatomic's configure fails. The config.log file is here:
>> https://gist.github.com/3931504
>>
>> I've recreated the conftest.c and ran the same command. The output is fine
>> a
Hi,
PRE bases on the result of value numbering (run_scc_vn). At the end,
it free_scc_vn. But before free_scc_vn, it might call cleanup_tree_cfg
();
if (do_eh_cleanup || do_ab_cleanup)
cleanup_tree_cfg ();
cleanup_tree_cfg might call make_ssa_name which might reuse some
"name" from the FREE
On Mon, Oct 22, 2012 at 6:25 PM, Steven Bosscher wrote:
> Bin.Cheng wrote:
>> It is possible to have register pressure decreased when hoisting an
>> expression up in flow graph because of shrunk live range of input
>> register operands.
>> To accurately simulating the change of register pressure,
On Mon, Oct 22, 2012 at 6:14 PM, Steven Bosscher wrote:
> Bin. Cheng wrote:
>> Quoting from GCCINT, section "9.5 RTL passes":
>> "When optimizing for size, GCSE is done using Morel-Renvoise Partial
>> Redundancy Elimination, with the exception that it does not try to
>> move invariants out of loop
On Oct 22, 2012, at 7:58 PM, Perry Smith wrote:
>
> On Oct 22, 2012, at 8:55 AM, Michael Haubenwallner wrote:
>
>> On 10/22/2012 03:49 PM, Perry Smith wrote:
>>> In stage 3, libatomic's configure fails. The config.log file is here:
>>> https://gist.github.com/3931504
>>>
>>> I've recreated t
On Oct 22, 2012, at 8:55 AM, Michael Haubenwallner wrote:
> On 10/22/2012 03:49 PM, Perry Smith wrote:
>> In stage 3, libatomic's configure fails. The config.log file is here:
>> https://gist.github.com/3931504
>>
>> I've recreated the conftest.c and ran the same command. The output is fine
In using 4.7.2 and am working on extending our distro to have
x86/x86_64/x32/arm
Ive yanked the H.Lu patch to add --with-abi support from trunk and am
extending it to
have a default 32bit ABI we have nicknamed this the LOTR compiler [One
compiler to compile them all] [for the i386 at least]
>>> In the following RTL, the hardware (reg:HI r2), whose natural mode is
>>> HImode, is set to 0, but when analysing the REG_EQUAL notes of the MULT
>>> insn during CSE pass, the (reg:SI r2) is computed to be equivalent to 0,
>>> which is wrong (the target is big endian).
>>>
>>> (insn 51 9 52 3
On Mon, Oct 22, 2012 at 9:49 AM, Perry Smith wrote:
> In stage 3, libatomic's configure fails. The config.log file is here:
> https://gist.github.com/3931504
>
> I've recreated the conftest.c and ran the same command. The output is fine
> and executes with a 0 status.
>
> The clue (that I can'
On 10/22/2012 12:59 AM, Bin.Cheng wrote:
Hi,
Quoting from GCCINT, section "9.5 RTL passes":
"When optimizing for size, GCSE is done using Morel-Renvoise Partial
Redundancy Elimination, with the exception that it does not try to
move invariants out of loops—that is left to the loop optimization
pa
Hi Guys,
The RX port is not currently building in the mainline sources because
of the following ICE:
libgcc/unwind-dw2-fde.c: In function 'add_fdes':
libgcc/unwind-dw2-fde.c:721:1: internal compiler error: in
variable_post_merge_new_vals, at var-tracking.c:4303
}
^
0x86f0bed variable
On 10/22/2012 03:49 PM, Perry Smith wrote:
> In stage 3, libatomic's configure fails. The config.log file is here:
> https://gist.github.com/3931504
>
> I've recreated the conftest.c and ran the same command. The output is fine
> and executes with a 0 status.
>
> The clue (that I can't figu
In stage 3, libatomic's configure fails. The config.log file is here:
https://gist.github.com/3931504
I've recreated the conftest.c and ran the same command. The output is fine and
executes with a 0 status.
The clue (that I can't figure out) is cc1 is a 32 bit program but it tried to
load th
>> In the following RTL, the hardware (reg:HI r2), whose natural mode is
>> HImode, is set to 0, but when analysing the REG_EQUAL notes of the MULT
>> insn during CSE pass, the (reg:SI r2) is computed to be equivalent to 0,
>> which is wrong (the target is big endian).
>>
>> (insn 51 9 52 3 (set (r
Bin.Cheng wrote:
> It is possible to have register pressure decreased when hoisting an
> expression up in flow graph because of shrunk live range of input
> register operands.
> To accurately simulating the change of register pressure, I have to
> check the change of live range of input operands du
Bin. Cheng wrote:
> Quoting from GCCINT, section "9.5 RTL passes":
> "When optimizing for size, GCSE is done using Morel-Renvoise Partial
> Redundancy Elimination, with the exception that it does not try to
> move invariants out of loops—that is left to the loop optimization
> pass. If MR PRE GCSE
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