Re: MIPS: 2'nd pass of ira, causes weird register allocation for 2-op mult

2012-05-28 Thread Richard Sandiford
Hi Vlad, Thanks for the answer. Vladimir Makarov writes: > On 05/28/2012 03:09 PM, Richard Sandiford wrote: >>Or is it a conceptual part of the algorithm? > No. >>More generally, >> what kind of situations does the second pass help with? > I can not show such situations right now but I d

Re: Fixincludes

2012-05-28 Thread Jonathan Wakely
On 29 May 2012 00:19, Jeremy Huntwork wrote: > Hello, > > I'm endeavoring to understand the history and purpose of the fixincludes > script. The README-fixinc states that the purpose is to fix > ANSI-incompatible headers which 'many vendors supply'. Is this really still > the case? Certainly by now

Fixincludes

2012-05-28 Thread Jeremy Huntwork
Hello, I'm endeavoring to understand the history and purpose of the fixincludes script. The README-fixinc states that the purpose is to fix ANSI-incompatible headers which 'many vendors supply'. Is this really still the case? Certainly by now this is very rare and corner cases should really b

Re: MIPS: 2'nd pass of ira, causes weird register allocation for 2-op mult

2012-05-28 Thread Vladimir Makarov
On 05/28/2012 03:09 PM, Richard Sandiford wrote: Klaus Pedersen writes: The summery goes something like this: It is possible for the second pass of ira to get confused and decide that NO_REGS or a hard float register are better choices for the result of the 2 operand mult. First pass already o

Re: MIPS: 2'nd pass of ira, causes weird register allocation for 2-op mult

2012-05-28 Thread Richard Sandiford
Klaus Pedersen writes: > The summery goes something like this: > > It is possible for the second pass of ira to get confused and decide that > NO_REGS or a hard float register are better choices for the result of the > 2 operand mult. First pass already optimally allocated in GR_AND_MD1_REGS. Yea