陳韋任 writes:
> Assume I want basic block register usage information, and
> I further assume that native machine has a register set
> {R0, R1, R2, R3}. The source code might be compiled into
> two basic blocks. What I want is something like,
>
>BB1 (0x100 - 0x120)
>In 0100
>
Hi, Ian
I will try my best to explain what I want. :-)
Assume I want basic block register usage information, and
I further assume that native machine has a register set
{R0, R1, R2, R3}. The source code might be compiled into
two basic blocks. What I want is something like,
BB1 (0x100
Hi!
I'm willing to translate publication located at
http://gcc.gnu.org/fortran to the Belorussian language (my mother
tongue). What I'm asking for is your written permission, so you don't
mind after I'll post the translation to my blog. The translation is
intended only for web, no print copie
On 05/16/2011 04:19 PM, Georg-Johann Lay wrote:
Pat Haugen schrieb:
I'm seeing some odd behavior in ira for PowerPC, starting with the big ira
merge best I can tell (r171649).
void foo(float *f1, float*f2) {
*f1 = *f2;
}
If I compile with gcc -S -m64 -O3 -mcpu=power7 and look at the ira dump
Pat Haugen schrieb:
I'm seeing some odd behavior in ira for PowerPC, starting with the big
ira merge best I can tell (r171649).
void foo(float *f1, float*f2) {
*f1 = *f2;
}
If I compile with gcc -S -m64 -O3 -mcpu=power7 and look at the ira dump,
I see that the pseudo used to copy the data,
I'm seeing some odd behavior in ira for PowerPC, starting with the big ira merge
best I can tell (r171649).
void foo(float *f1, float*f2) {
*f1 = *f2;
}
If I compile with gcc -S -m64 -O3 -mcpu=power7 and look at the ira dump, I see
that the pseudo used to copy the data, r120, is spilled. Rel
陳韋任 writes:
> I found a gcc plugin called gcc-vcg-plugin
> (http://code.google.com/p/gcc-vcg-plugin/). I am not sure
> if this can be a start point.
>
> Any comments? Thanks.
I honestly don't know whether you can use that as a starting point,
because I don't know what you actually want to do
It looks like the machinery that picks MIPS branch-likely instructions (on
processors that don't object to them) is driven purely by their delay slot
annul properties and not at all by branch probability.
That brings up a couple of questions.
1. Assuming it doesn't matter to the delay slot fill
Hi all,
I am trying to add support for hardware loops for a 32bit target. In
the target QImode is 32bit. The loop counter used in hardware loop
construct is 17bit address registers. This is represented using
PQImode. Since mode for the doloop pattern is found out after loop
discovery it need not b
Hi, Ian
I found a gcc plugin called gcc-vcg-plugin
(http://code.google.com/p/gcc-vcg-plugin/). I am not sure
if this can be a start point.
Any comments? Thanks.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Te
On 16 May 2011 01:06, Kyle Markley wrote:
> A few months ago I managed to build gcc 4.5.1 on an OpenBSD x86_64
> platform. This was difficult, even with the patches available in my
> system's ports tree (which could build gcc 4.3). I would like to volunteer
> to make this platform better support
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