Performance optimizations for Intel Core 2 and Core i7 processors

CodeSourcery is working on improving performance for Intel's Core 2 and Core i7 families of processors. CodeSourcery plans to add support for unaligned vector instructions, to provide fine-tuned scheduling support and to update instruction selection and instruction cost models for Core i7 and

lto and compile flag associations

What is the current LTO design with regards to the retention of compiler flags during the actual link time optimization compilation steps. For example, if one is linking mixed fortran and c object files which have distinct flags passed in FFLAGS and CFLAGS, are these embedded with the LTO inform

Re: Clobbering two registers

On Wed, May 12, 2010 at 6:43 PM, Ian Lance Taylor wrote: > > Yes. > > Also look at match_scratch. > I assume that I only need to setup two match_scratch then, right? -- PMatos

gcc-4.3-20100516 is now available

Snapshot gcc-4.3-20100516 is now available on ftp://gcc.gnu.org/pub/gcc/snapshots/4.3-20100516/ and on various mirrors, see http://gcc.gnu.org/mirrors.html for details. This snapshot has been generated from the GCC 4.3 SVN branch with the following options: svn://gcc.gnu.org/svn/gcc/branches