On Wed, Nov 6, 2019 at 1:13 AM Brian Masney wrote:
>
> On Tue, Nov 05, 2019 at 08:23:27AM -0800, Rob Clark wrote:
> > On Tue, Nov 5, 2019 at 2:08 AM Brian Masney wrote:
> > > The 'pp done time out' errors go away if I revert the following three
> > > com
On Wed, Nov 6, 2019 at 8:47 AM Jeffrey Hugo wrote:
>
> On Wed, Nov 6, 2019 at 9:30 AM Rob Clark wrote:
> >
> > On Wed, Nov 6, 2019 at 1:13 AM Brian Masney wrote:
> > >
> > > On Tue, Nov 05, 2019 at 08:23:27AM -0800, Rob Clark wrote:
> > >
On Thu, Nov 7, 2019 at 3:10 AM Brian Masney wrote:
>
> On Wed, Nov 06, 2019 at 08:58:59AM -0800, Rob Clark wrote:
> > On Wed, Nov 6, 2019 at 8:47 AM Jeffrey Hugo
> > wrote:
> > >
> > > On Wed, Nov 6, 2019 at 9:30 AM Rob Clark wrote:
> > > >
>
iled or tiled+ubwc format in
the first place.. and code that does understand it, knows enough to
know that tiled/tiled+ubwc is always in the native component order.
> Signed-off-by: Fritz Koenig
Reviewed-by: Rob Clark
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c| 18 ++
On Thu, Nov 7, 2019 at 9:40 AM Jeffrey Hugo wrote:
>
> On Thu, Nov 7, 2019 at 9:17 AM Rob Clark wrote:
> >
> > On Thu, Nov 7, 2019 at 3:10 AM Brian Masney wrote:
> > >
> > > On Wed, Nov 06, 2019 at 08:58:59AM -0800, Rob Clark wrote:
> > >
lease() is ignored.
> > > >
> > > > Fixes: 4f776f4511c7 ("drm/msm/gpu: Convert the GPU show function to use
> > > > the GPU state")
> > > > Cc: stable # 4.18
> > > > Cc: Jordan Crouse
> > > > Cc: Rob Clark
>
On Thu, Nov 14, 2019 at 2:16 AM Harigovindan P wrote:
>
> Add DSI config changes to support DSI version.
>
> Signed-off-by: Harigovindan P
Reviewed-by: Rob Clark
For patch 1/2 with the panel driver, probably best to split that out
into a different patch(set), since panel driver
On Thu, Nov 14, 2019 at 2:17 AM Harigovindan P wrote:
>
> Add support for Visionox panel driver.
>
> Signed-off-by: Harigovindan P
> ---
> drivers/gpu/drm/panel/Kconfig | 9 +
> drivers/gpu/drm/panel/Makefile | 1 +
> drivers/gpu/drm/panel/panel-visionox-rm69
From: Rob Clark
This isn't an error. Also the clk APIs handle the NULL case, so we can
just delete the check.
Signed-off-by: Rob Clark
Tested-by: Matthias Kaehlcke
---
drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c | 26 ++---
1 file changed, 7 insertions(+), 19 dele
On Mon, Nov 18, 2019 at 3:44 AM Kalyan Thota wrote:
>
> Add changes to setup display datapath on SC7180 target
>
> changes in v1:
> 1) add changes to support ctl_active on SC7180 target
> 2) while selecting the number of mixers in the topology
> consider the interface width.
>
> This patch has dep
From: Rob Clark
Previously, if the freq were overriden (ie. via sysfs), it would get
reset to max on resume.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++--
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +++
2 files changed, 9 insertions(+), 2 deletions(-)
diff
On Mon, Nov 18, 2019 at 4:32 PM Stephen Boyd wrote:
>
> Quoting Rob Clark (2019-11-18 15:40:38)
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
> > b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
> > index 39a26dd63674..2af91ed7ed0c 100644
> > --- a/drivers/gpu/drm/m
me to revisit the
struct_mutex usage since we moved to per-object-locks.. the downside,
I suppose, of kernel generally working ok and this not being a big
enough fire to bubble up to the top of my todo list
BR,
-R
>
> Signed-off-by: Daniel Vetter
> Cc: Rob Clark
> Cc: Sean Paul
>
using struct_mutex, it seems to be using
> dma_resv_lock for general buffer state protection?
>
> v2:
> - Add comment to explain why the ww ticket setup is separate (Rob)
> - Fix up error handling, we need to make sure we don't call
> ww_acquire_fini without _init.
>
>
From: Rob Clark
We can have two cases, when it comes to "zap" fw. Either the fw
requires zap fw to take the GPU out of secure mode at boot, or it does
not and we can write RBBM_SECVID_TRUST_CNTL directly. Previously we
decided based on whether zap fw load succeeded, but this is n
On Thu, Nov 28, 2019 at 10:56 PM Harigovindan P wrote:
>
> Add a compatible string to support sc7180 panel version.
>
> Signed-off-by: Harigovindan P
> ---
> .../bindings/display/visionox,rm69299.txt | 68
> ++
> 1 file changed, 68 insertions(+)
> create mode 10075
On Mon, Jul 1, 2019 at 7:03 AM Rob Herring wrote:
>
> On Sun, Jun 30, 2019 at 2:36 PM Rob Clark wrote:
> >
> > From: Rob Clark
> >
> > The panel-id property in chosen can be used to communicate which panel,
> > of multiple possibilities, is install
On Sat, Nov 30, 2019 at 10:37 AM Rob Clark wrote:
>
> On Mon, Jul 1, 2019 at 7:03 AM Rob Herring wrote:
> >
> > On Sun, Jun 30, 2019 at 2:36 PM Rob Clark wrote:
> > >
> > > From: Rob Clark
> > >
> > > The panel-id property in chosen can
On Mon, Dec 2, 2019 at 5:47 AM Chandan Uddaraju wrote:
>
> These patches are to enable DisplayPort driver on SanpDragon.
>
> These patches have dependency on clock driver changes that
> provide DP clock support.
This looks like just a functional/runtime dependency? Ie. it would
only be the corre
On Mon, Dec 2, 2019 at 5:48 AM Chandan Uddaraju wrote:
>
> Add the needed displayPort files to enable DP driver
> on msm target.
>
> "dp_display" module is the main module that calls into
> other sub-modules. "dp_drm" file represents the interface
> between DRM framework and DP driver.
>
> changes
On Thu, Nov 28, 2019 at 11:41 PM Sharat Masetty wrote:
>
> Add GBIF register definitions required to implement a618
> GPU revision
>
> Signed-off-by: Sharat Masetty
thanks, I've pushed the xml to envytools
BR,
-R
> ---
> rnndb/adreno/a6xx.xml | 26 ++
> 1 file changed,
On Mon, Dec 2, 2019 at 5:48 AM Chandan Uddaraju wrote:
>
> Add the needed displayPort files to enable DP driver
> on msm target.
>
> "dp_display" module is the main module that calls into
> other sub-modules. "dp_drm" file represents the interface
> between DRM framework and DP driver.
>
> changes
rs are merged into
> drm-next via a different tree(Rob Clark).
>
> Signed-off-by: Harigovindan P
Reviewed-by: Rob Clark
> ---
> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 21 +
> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
> 2 files changed, 22 insertions(+)
&
On Tue, Dec 3, 2019 at 7:23 AM Sharat Masetty wrote:
>
> Fix the cx debugbus related register configuration, to collect accurate
> bus data during gpu snapshot. This helps with complete snapshot dump
> and also complete proper GPU recovery.
>
> Signed-off-by: Sharat Masetty
fwiw, this one we alr
visionox panel driver code out into a
> >different patch(set), since panel drivers are merged into
> >drm-next via a different tree(Rob Clark).
>
> The change log shouldn't be part of the commit message, please place it
> after the '---' separator
arate
attach step. I suppose we probably should do a similar cleanup for
mmu->detach(), but I guess that can be it's own patch
Reviewed-by: Rob Clark
> ---
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
> drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 4 -
zation
> if they need it.
>
> Signed-off-by: Jordan Crouse
Reviewed-by: Rob Clark
> ---
>
> drivers/gpu/drm/msm/adreno/a2xx_gpu.c| 16 ++
> drivers/gpu/drm/msm/adreno/a3xx_gpu.c| 1 +
> drivers/gpu/drm/msm/adreno/a4xx_gpu.c| 1 +
> drivers/gpu/drm/msm
On Fri, Nov 22, 2019 at 3:32 PM Jordan Crouse wrote:
>
> Attempt to enable split pagetables if the arm-smmu driver supports it.
> This will move the default address space from the default region to
> the address range assigned to TTBR1. The behavior should be transparent
> to the driver for now bu
driver for now but it gets the default buffers out of the way
> when we want to start swapping TTBR0 for context-specific pagetables.
>
> Signed-off-by: Jordan Crouse
Reviewed-by: Rob Clark
(my previous r-b's on the other patches from v2 carries over to v3)
> ---
>
> driv
On Thu, Jan 2, 2020 at 3:02 AM Sharat Masetty wrote:
>
> From: Vivek Gautam
>
> Add iommu domain attribute for using system cache aka last level
> cache on QCOM SoCs by client drivers like GPU to set right
> attributes for caching the hardware pagetables into the system cache.
>
> Signed-off-by:
From: Rob Clark
Since zap firmware can be device specific, allow for a firmware-name
property in the zap node to specify which firmware to load, similarly to
the scheme used for dsp/wifi/etc.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 32
From: Rob Clark
The firmware-name property in the zap node can be used to specify a
device specific zap firmware.
Signed-off-by: Rob Clark
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display
From: Rob Clark
We want to specify per-device firmware-name, so move the zap node into
the .dts file for individual boards/devices. This lets us get rid of
the /delete-node/ for cheza, which does not use zap.
Signed-off-by: Rob Clark
---
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
From: Rob Clark
For devices which use zap fw to take the GPU out of secure mode on
reset, the firmware is likely to be signed with a device specific key.
Meaning that we can't have a single filesystem (or /lib/firmware) that
works on multiple devices.
So allow a firmware-name to be specifi
On Wed, Jan 8, 2020 at 7:38 AM Tom Rix wrote:
>
>
> On 1/7/20 5:38 PM, Rob Clark wrote:
> > From: Rob Clark
> >
> > Since zap firmware can be device specific, allow for a firmware-name
> > property in the zap node to specify which firmware to load, similarly to
On Wed, Jan 8, 2020 at 8:30 AM Rob Clark wrote:
>
> On Wed, Jan 8, 2020 at 7:38 AM Tom Rix wrote:
> >
> >
> > On 1/7/20 5:38 PM, Rob Clark wrote:
> > > From: Rob Clark
> > >
> > > Since zap firmware can be device specific, allow for a firm
From: Rob Clark
For newer devices we want to require the path to come from the
firmware-name property in the zap-shader dt node.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a
From: Rob Clark
We want to specify per-device firmware-name, so move the zap node into
the .dts file for individual boards/devices. This lets us get rid of
the /delete-node/ for cheza, which does not use zap.
Signed-off-by: Rob Clark
---
v2: use 'sdm845' for subdir for devices tha
From: Rob Clark
Since zap firmware can be device specific, allow for a firmware-name
property in the zap node to specify which firmware to load, similarly to
the scheme used for dsp/wifi/etc.
v2: only need a single error msg when we can't load from firmware-name
specified path, an
From: Rob Clark
The firmware-name property in the zap node can be used to specify a
device specific zap firmware.
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a
From: Rob Clark
For devices which use zap fw to take the GPU out of secure mode on
reset, the firmware is likely to be signed with a device specific key.
Meaning that we can't have a single filesystem (or /lib/firmware) that
works on multiple devices.
So allow a firmware-name to be specifi
On Mon, Jan 13, 2020 at 7:37 AM Brian Ho wrote:
>
> Implements an ioctl to wait until a value at a given iova is greater
> than or equal to a supplied value.
>
> This will initially be used by turnip (open-source Vulkan driver for
> QC in mesa) for occlusion queries where the userspace driver can
On Mon, Jan 13, 2020 at 9:51 AM Jordan Crouse wrote:
>
> On Mon, Jan 13, 2020 at 10:36:05AM -0500, Brian Ho wrote:
> > Implements an ioctl to wait until a value at a given iova is greater
> > than or equal to a supplied value.
> >
> > This will initially be used by turnip (open-source Vulkan drive
On Mon, Jan 13, 2020 at 9:55 AM Jordan Crouse wrote:
>
> On Mon, Jan 13, 2020 at 10:36:04AM -0500, Brian Ho wrote:
> > This wait queue is signaled on all IRQs for a given GPU and will be
> > used as part of the new MSM_WAIT_IOVA ioctl so userspace can sleep
> > until the value at a given iova reac
On Mon, Jan 13, 2020 at 2:55 PM Brian Ho wrote:
>
> On Mon, Jan 13, 2020 at 09:57:43AM -0800, Kristian Kristensen wrote:
> > On Mon, Jan 13, 2020 at 8:25 AM Rob Clark wrote:
> >
> > > On Mon, Jan 13, 2020 at 7:37 AM Brian Ho wrote:
> > > >
> > >
On Tue, Jan 14, 2020 at 7:58 AM Jordan Crouse wrote:
>
> On Tue, Jan 14, 2020 at 01:40:11AM +0100, Bas Nieuwenhuizen wrote:
> > On Tue, Jan 14, 2020 at 12:41 AM Jordan Crouse
> > wrote:
> > >
> > > On Mon, Jan 13, 2020 at 09:25:57PM +0100, Bas Nieuwenhuizen wrote:
> > > > This
> > > >
> > > > 1)
On Tue, Jan 14, 2020 at 8:40 AM Brian Ho wrote:
>
> On Mon, Jan 13, 2020 at 03:17:38PM -0800, Rob Clark wrote:
> > On Mon, Jan 13, 2020 at 2:55 PM Brian Ho wrote:
> > >
> > > On Mon, Jan 13, 2020 at 09:57:43AM -0800, Kristian Kristensen wrote:
> > > >
On Mon, Jan 13, 2020 at 9:51 AM Jordan Crouse wrote:
>
> On Mon, Jan 13, 2020 at 10:36:05AM -0500, Brian Ho wrote:
> > +
> > + vaddr = base_vaddr + args->offset;
> > +
> > + /* Assumes WC mapping */
> > + ret = wait_event_interruptible_timeout(
> > + gpu->event, *va
_encoder_enable
Rob Clark (7):
drm/msm/dpu: ignore NULL clocks
drm/msm/a6xx: restore previous freq on resume
drm/msm/adreno: fix zap vs no-zap handling
drm/msm/dsi: split clk rate setting and enable
drm/msm: support firmware-name for zap fw (v2)
drm/msm: allow
ported-by: Stephen Boyd
> Signed-off-by: Sean Paul
> Tested-by: Stephen Boyd
> Signed-off-by: Douglas Anderson
> ---
> This patch has been floating in the ether for over a year [1]. I know
> next to nothing about it, but I'm told it's still useful so I'm
>
On Wed, Jan 22, 2020 at 6:51 AM Sean Paul wrote:
>
> On Tue, Jan 21, 2020 at 11:26:05AM -0800, Rob Clark wrote:
> > On Tue, Jan 21, 2020 at 11:19 AM Douglas Anderson
> > wrote:
> > >
> > > From: Sean Paul
> > >
> > > Turning on
his fixes the UBWC issues on a618
Fixes: e812744c5f95 ("drm: msm: a6xx: Add support for A618")
Reviewed-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno
On Mon, Feb 3, 2020 at 4:21 PM John Stultz wrote:
>
> On Wed, Jan 22, 2020 at 11:19 PM Sharat Masetty
> wrote:
> >
> > This patch adds support for enabling Graphics Bus Interface(GBIF)
> > used in multiple A6xx series chipets. Also makes changes to the
> > PDC/RSC sequencing specifically require
+jstultz
On Tue, Feb 4, 2020 at 9:42 AM Jordan Crouse wrote:
>
> Commit e812744c5f95 ("drm: msm: a6xx: Add support for A618") added a
> universal GBIF un-halt into a6xx_start(). This can cause problems for
> a630 targets which do not use GBIF and might have access protection
> enabled on the regi
t
> GMU idle.
>
> Move a6xx_bus_clear_pending_transactions to a6xx_gmu.c and use it in
> the appropriate place in the shutdown routine and remove the redundant
> idle call.
>
> v2: Remove newly unused variable that was triggering a warning
>
> Signed-off-by: Jordan Crouse
Reviewed-by:
there
are several different SoCs with a618.. but for now, this looks
reasonable
Reviewed-by: Rob Clark
Fixes: e812744c5f95 ("drm: msm: a6xx: Add support for A618")
> ---
>
> drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 85
> ---
> 1 file changed,
GBIF is open for business when we restart the hardware.
>
> Signed-off-by: Jordan Crouse
Reviewed-by: Rob Clark
Fixes: e812744c5f95 ("drm: msm: a6xx: Add support for A618")
> ---
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12
> 1 file changed, 12
On Fri, Jan 31, 2020 at 12:00 AM Akhil P Oommen wrote:
>
> On 1/24/2020 11:56 PM, Jordan Crouse wrote:
> > On Fri, Jan 24, 2020 at 05:50:11PM +0530, Akhil P Oommen wrote:
> >> Highest bank bit configuration is different for a618 gpu. Update
> >> it with the correct configuration which is the reset
On Mon, Feb 10, 2020 at 9:58 PM wrote:
>
> On 2020-02-07 19:40, Jeffrey Hugo wrote:
> > On Fri, Feb 7, 2020 at 5:38 AM wrote:
> >>
> >> On 2020-02-06 20:29, Jeffrey Hugo wrote:
> >> > On Thu, Feb 6, 2020 at 2:13 AM Harigovindan P
> >> > wrote:
> >> >>
> >> >> For a given byte clock, if VCO recal
On Tue, Feb 11, 2020 at 7:59 AM Jeffrey Hugo wrote:
>
> On Tue, Feb 11, 2020 at 8:44 AM Rob Clark wrote:
> >
> > On Mon, Feb 10, 2020 at 9:58 PM wrote:
> > >
> > > On 2020-02-07 19:40, Jeffrey Hugo wrote:
> > > > On Fri, Feb 7, 2020 at 5:38
On Tue, Feb 11, 2020 at 8:05 PM Jeffrey Hugo wrote:
>
> On Tue, Feb 11, 2020 at 5:28 PM Rob Clark wrote:
> >
> > On Tue, Feb 11, 2020 at 7:59 AM Jeffrey Hugo
> > wrote:
> > >
> > > On Tue, Feb 11, 2020 at 8:44 AM Rob Clark wrote:
> > &g
From: Rob Clark
The component order between the two was swapped, resulting in incorrect
color when games with 565 visual hit the overlay path instead of GPU
composition.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm
tables for sc7180
drm/msm: Fix a6xx GMU shutdown sequence
Kalyan Thota (1):
msm:disp:dpu1: add UBWC support for display on SC7180
Rob Clark (1):
drm/msm/dpu: fix BGR565 vs RGB565 confusion
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 37 +++--
drivers/gpu/drm/msm/adreno/
From: Rob Clark
Also log buffers with the DUMP flag set, to ensure we capture all useful
cmdstream in crashdump state with modern mesa.
Otherwise we miss out on the contents of "state object" cmdstream
buffers.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_
From: Rob Clark
Also log buffers with the DUMP flag set, to ensure we capture all useful
cmdstream in crashdump state with modern mesa.
Otherwise we miss out on the contents of "state object" cmdstream
buffers.
v2: add missing 'inline'
Signed-off-by: Rob Clark
---
On Sun, Feb 9, 2020 at 11:41 PM Sharat Masetty wrote:
>
> This patch adds the required dt nodes and properties
> to enabled A618 GPU.
>
> Signed-off-by: Sharat Masetty
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 102
> +++
> 1 file changed, 102 insertions(+)
>
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
index 68cccfa2870a..bbbec8d26870 100644
--- a
On Tue, Feb 25, 2020 at 11:33 AM Stephen Boyd wrote:
>
> Quoting Drew Davenport (2020-02-19 09:42:25)
> > Make iterator implementation private, and add function to
> > query resources assigned to an encoder.
> >
> > Signed-off-by: Drew Davenport
>
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dp
On Tue, Feb 25, 2020 at 3:54 PM John Stultz wrote:
>
> On Thu, Feb 20, 2020 at 10:27 AM Jordan Crouse wrote:
> >
> > The GMU has very few memory allocations and uses a flat memory space so
> > there is no good reason to go out of our way to bypass the DMA APIs which
> > were basically designed fo
On Mon, Mar 9, 2020 at 4:18 AM Brian Masney wrote:
>
> The sram property was incorrectly added to the GMU binding when it
> really belongs with the GPU binding instead. Let's go ahead and
> move it.
>
> While changes are being made here, let's update the sram property
> description to mention that
ixes: 3ef2f119bd3ed (drm/msm: Use drm_attach_bridge() to attach a bridge to
> an encoder)
> Cc: Boris Brezillon
> Signed-off-by: Ilia Mirkin
Thanks
Reviewed-by: Rob Clark
> ---
> drivers/gpu/drm/msm/edp/edp.c | 4
> drivers/gpu/drm/msm/hdmi/hdmi.c | 4
> 2 f
On Mon, Mar 16, 2020 at 4:05 AM Kalyan Thota wrote:
>
> "The PM core always increments the runtime usage counter
> before calling the ->suspend() callback and decrements it
> after calling the ->resume() callback"
>
> DPU and DSI are managed as runtime devices. When
> suspend is triggered, PM core
On Wed, Mar 18, 2020 at 9:39 PM Bjorn Andersson
wrote:
>
> With the introduction of '3ef2f119bd3e ("drm/msm: Use
> drm_attach_bridge() to attach a bridge to an encoder")' the HDMI bridge
> is attached both in msm_hdmi_bridge_init() and later in
> msm_hdmi_modeset_init().
>
> The second attempt fai
: display: msm: Convert GMU bindings to YAML
drm/msm/a6xx: Use the DMA API for GMU memory objects
Pavel Machek (1):
drm/msm: fix leaks if initialization fails
Rob Clark (2):
drm/msm: devcoredump should dump MSM_SUBMIT_BO_DUMP buffers
drm/msm/a6xx: Fix CP_MEMPOOL state name
was not getting called
> > and it kept the clocks on which resulted in target not
> > entering into XO shutdown.
> >
> > Add changes to manage runtime devices during pm sleep.
> >
> > Changes in v1:
> > - Remove unnecessary checks in the function
> > _
On Mon, Apr 20, 2020 at 12:59 PM Jonathan Marek wrote:
>
> On 4/20/20 3:51 PM, Bjorn Andersson wrote:
> > On Mon 20 Apr 07:03 PDT 2020, Jonathan Marek wrote:
> >
> >> This reverts commit a5fb8b918920c6f7706a8b5b8ea535a7f077a7f6.
> >
> > Why?
> >
>
> It removes something I need for the next patches
T_BO_DUMP
> buffers")
> Reported-by: Stephen Rothwell
> Signed-off-by: Bjorn Andersson
thanks,
Reviewed-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_rd.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_rd.c b/
ly also disallow get_vaddr() on imported buffers.
BR,
-R
>
> But even if that WARN_ON is wrong, cleaning up a vmap() done by msm by
> calling dma_buf_vmap is the wrong thing to do.
>
> Signed-off-by: Daniel Vetter
> Cc: Rob Clark
> Cc: Sean Paul
> Cc: linux-arm-...@vg
On Mon, May 11, 2020 at 8:29 AM Daniel Vetter wrote:
>
> On Mon, May 11, 2020 at 5:24 PM Rob Clark wrote:
> >
> > On Mon, May 11, 2020 at 2:36 AM Daniel Vetter
> > wrote:
> > >
> > > I honestly don't exactly understand what's going on he
On Mon, May 18, 2020 at 7:23 AM Jordan Crouse wrote:
>
> On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote:
> > This patches replaces the previously used static DDR vote and uses
> > dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling
> > GPU frequency.
> >
> > Signed-o
On Sat, May 23, 2020 at 12:23 AM Shawn Guo wrote:
>
> On Fri, May 22, 2020 at 04:03:14PM -0600, Jordan Crouse wrote:
> > diff --git a/drivers/gpu/drm/msm/msm_gpummu.c
> > b/drivers/gpu/drm/msm/msm_gpummu.c
> > index 34980d8eb7ad..0ad0f848560a 100644
> > --- a/drivers/gpu/drm/msm/msm_gpummu.c
> >
Hi Dave,
Not too huge this time around, but a bunch of interesting new
stuff:
* new gpu support: a405, a640, a650
* dpu: clock and bandwidth scaling
* dpu: color processing support
* mdp5: support for msm8x36 (the thing with a405)
* some prep work for per-context pagetables (ie the part that
On Wed, May 27, 2020 at 1:47 AM Sharat Masetty wrote:
>
> + more folks
>
> On 5/18/2020 9:55 PM, Rob Clark wrote:
> > On Mon, May 18, 2020 at 7:23 AM Jordan Crouse
> > wrote:
> >> On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote:
> >>&
the wrong thing to do.
>
> v2: Rob said in review that we do indeed have a gap in get_vaddr() that
> needs to be plugged. But the users I've found aren't legit users on
> imported dma-buf, so we can just reject that.
>
> Signed-off-by: Daniel Vetter
> Cc: Rob Clark
&g
From: Rob Clark
This is causing multiple armv7 missing do_div() errors, so lets drop it
for now.
This reverts commit 04d9044f6c577948609c03b4e33b8fbc8b87c4b1.
Cc: Kalyan Thota
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 106 +++---
.../gpu/drm
(1):
drm/msm/dpu: update bandwidth threshold check
Rob Clark (1):
Revert "drm/msm/dpu: add support for clk and bw scaling for display"
Roy Spliet (1):
drm/msm/mdp5: Fix mdp5_init error path for failed mdp5_kms allocation
Shawn Guo (2):
drm/msm/a4xx: add adr
On Thu, Jun 4, 2020 at 1:57 PM Jordan Crouse wrote:
>
> Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
> split pagetables.
>
> Signed-off-by: Jordan Crouse
> ---
>
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
On Thu, Jun 4, 2020 at 3:02 PM Jordan Crouse wrote:
>
> On Thu, Jun 04, 2020 at 02:27:21PM -0700, Rob Clark wrote:
> > On Thu, Jun 4, 2020 at 1:57 PM Jordan Crouse wrote:
> > >
> > > Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
> > &g
On Mon, Jun 8, 2020 at 3:37 PM John Stultz wrote:
>
> On Mon, Jun 8, 2020 at 3:25 PM John Stultz wrote:
> >
> > On Wed, Mar 25, 2020 at 1:17 AM Kalyan Thota
> > wrote:
> > >
> > > This change adds support to configure dspp blocks in
> > > the dpu driver.
> > >
> > > Macro description of the cha
On Tue, Jun 9, 2020 at 5:48 AM Linus Walleij wrote:
>
> On Tue, May 5, 2020 at 10:27 AM Linus Walleij
> wrote:
> > On Wed, Apr 8, 2020 at 9:15 PM Arnd Bergmann wrote:
> >
> > > I ran into a randconfig link error with debugfs disabled:
> > >
> > > arm-linux-gnueabi-ld:
> > > drivers/gpu/drm/msm/
On Thu, Jun 11, 2020 at 5:55 AM Krishna Manikandan
wrote:
>
> From: Kalyan Thota
>
> Request for color processing blocks only if they are
> available in the display hw catalog and they are
> sufficient in number for the selection.
>
I believe this should have:
Fixes: e47616df008b ("drm/msm/dpu:
On Thu, Jun 11, 2020 at 3:29 PM Jordan Crouse wrote:
>
> Add support for using per-instance pagetables if all the dependencies are
> available.
>
> Signed-off-by: Jordan Crouse
> ---
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 69 ++-
> drivers/gpu/drm/msm/msm_ringbuffer.
On Wed, Jun 17, 2020 at 1:53 PM Eric Anholt wrote:
>
> Previously the address space went from 16M to ~0u, but with the
> refactor one of the 'f's was dropped, limiting us to 256MB.
> Additionally, the new interface takes a start and size, not start and
> end, so we can't just copy and paste.
>
> F
On Fri, Jun 5, 2020 at 9:26 PM Sharat Masetty wrote:
>
> This patch changes the plumbing to send the devfreq recommended opp rather
> than the frequency. Also consolidate and rearrange the code in a6xx to set
> the GPU frequency and the icc vote in preparation for the upcoming
> changes for GPU->D
always, hides references to the
> nents and orig_nents entries, making the code robust, easier to follow
> and copy/paste safe.
>
> Signed-off-by: Marek Szyprowski
Acked-by: Rob Clark
(let me know if you want me to take this one in via msm-next or if the
plan is to tak
Commit: Rob Clark
CommitDate: Thu Jun 11 20:07:21 2020 -0700
drm/msm/dpu: fix error return code in dpu_encoder_init
Fix to return negative error code -ENOMEM with the use of
ERR_PTR from dpu_encoder_init.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Sig
On Wed, Jun 24, 2020 at 4:57 AM Kalyan Thota wrote:
>
> This change enables dither block for primary interface
> in display.
>
> Enabled for 6bpc in the current version.
>
> Signed-off-by: Kalyan Thota
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 45 +
> drivers/gpu/
Hi Dave,
A few fixes, mostly fallout from the address space refactor and dpu
color processing.
The following changes since commit 1cb2c4a2c89b2004a36399860c85a1af9b3fcba7:
Revert "drm/msm/dpu: add support for clk and bw scaling for display"
(2020-06-01 20:56:18 -0700)
are available in the Gi
(retry with $subject)
Hi Dave,
A few fixes, mostly fallout from the address space refactor and dpu
color processing.
The following changes since commit 1cb2c4a2c89b2004a36399860c85a1af9b3fcba7:
Revert "drm/msm/dpu: add support for clk and bw scaling for display"
(2020-06-01 20:56:18 -0700)
On Fri, Jun 26, 2020 at 1:01 PM Jordan Crouse wrote:
>
> Use the aperture settings from the IOMMU domain to set up the virtual
> address range for the GPU. This allows us to transparently deal with
> IOMMU side features (like split pagetables).
>
> Signed-off-by: Jordan Crouse
> ---
>
> drivers/
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