->core_initialized = false form dp_pm_suspend.
Changes in v15:
-- remove core_initialized flag check at both host_init and host_deinit
Fixes: 8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon
Chipsets")
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_ct
ommit text
Changes in v10:
-- group into one series
Changes in v11:
-- drop drm/msm/dp: dp_link_parse_sink_count() return immediately if aux read
Fixes: 7948fe12d47 ("drm/msm/dp: return correct edid checksum after corrupted
edid checksum read")
Signee-off-by: Kuogee Hsieh
Reviewed
From: Kuogee Hsieh
Some DP sinkers prefer to use tps4 instead of tps3 during training #2.
This patch will use tps4 to perform link training #2 if sinker's DPCD
supports it.
Changes in V2:
-- replace dp_catalog_ctrl_set_pattern() with
dp_catalog_ctrl_set_pattern_state_bit()
Changes
ining until video is
ready")
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index f98df93..245e1b9 100644
--- a/drivers/gpu/
On 1/14/2022 1:41 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-01-14 13:11:47)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index 7cc4d21..7cd6222 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
From: Kuogee Hsieh
Some DP sinkers prefer to use tps4 instead of tps3 during training #2.
This patch will use tps4 to perform link training #2 if sinker's DPCD
supports it.
Changes in V2:
-- replace dp_catalog_ctrl_set_pattern() with
dp_catalog_ctrl_set_pattern_state_bit()
Changes
ommit text
Changes in v10:
-- group into one series
Changes in v11:
-- drop drm/msm/dp: dp_link_parse_sink_count() return immediately if aux read
Fixes: 7948fe12d47 ("drm/msm/dp: return correct edid checksum after corrupted
edid checksum read")
Signee-off-by: Kuogee Hsieh
Reviewed
apdragon
Chipsets")
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_ctrl.c| 80 --
drivers/gpu/drm/msm/dp/dp_ctrl.h| 8 +--
drivers/gpu/drm/msm/dp/dp_display.c | 98 -
3 files changed, 89 insertions(+),
Group below 4 dp driver related patches into one series.
Kuogee Hsieh (4):
drm/msm/dp: do not initialize phy until plugin interrupt received
drm/msm/dp: populate connector of struct dp_panel
drm/msm/dp: add support of tps4 (training pattern 4) for HBR3
drm/msm/dp: stop link training
ining until video is
ready")
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index f98df93..245e1b9 100644
--- a/drivers/gpu/
ining until video is
ready")
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index f98df93..245e1b9 100644
--- a/drivers/gpu/
Group below 4 dp driver related patches into one series.
Kuogee Hsieh (4):
drm/msm/dp: do not initialize phy until plugin interrupt received
drm/msm/dp: populate connector of struct dp_panel
drm/msm/dp: add support of tps4 (training pattern 4) for HBR3
drm/msm/dp: stop link training
From: Kuogee Hsieh
Some DP sinkers prefer to use tps4 instead of tps3 during training #2.
This patch will use tps4 to perform link training #2 if sinker's DPCD
supports it.
Changes in V2:
-- replace dp_catalog_ctrl_set_pattern() with
dp_catalog_ctrl_set_pattern_state_bit()
Changes
ommit text
Changes in v10:
-- group into one series
Changes in v11:
-- drop drm/msm/dp: dp_link_parse_sink_count() return immediately if aux read
Fixes: 7948fe12d47 ("drm/msm/dp: return correct edid checksum after corrupted
edid checksum read")
Signee-off-by: Kuogee Hsieh
Reviewed
ute attention_cb()
Fixes: 8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon
Chipsets")
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_ctrl.c| 80 +++-
drivers/gpu/drm/msm/dp/dp_ctrl.h| 8 +--
drivers/gpu/drm/msm/dp/dp_di
On 1/14/2022 5:13 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-01-14 16:58:32)
@@ -1363,14 +1368,14 @@ static int dp_pm_suspend(struct device *dev)
if (dp_power_clk_status(dp->power, DP_CTRL_PM))
dp_ctrl_off_link_stream(dp-&g
Group below 4 dp driver related patches into one series.
Kuogee Hsieh (4):
drm/msm/dp: do not initialize phy until plugin interrupt received
drm/msm/dp: populate connector of struct dp_panel
drm/msm/dp: add support of tps4 (training pattern 4) for HBR3
drm/msm/dp: stop link training after
ute attention_cb()
Changes in v18:
-- remove core_initialized checking at dp_pm_suspend
Fixes: 8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon
Chipsets")
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_ctrl.c| 80 ++
drivers/g
ommit text
Changes in v10:
-- group into one series
Changes in v11:
-- drop drm/msm/dp: dp_link_parse_sink_count() return immediately if aux read
Fixes: 7948fe12d47 ("drm/msm/dp: return correct edid checksum after corrupted
edid checksum read")
Signee-off-by: Kuogee Hsieh
Reviewed
From: Kuogee Hsieh
Some DP sinkers prefer to use tps4 instead of tps3 during training #2.
This patch will use tps4 to perform link training #2 if sinker's DPCD
supports it.
Changes in V2:
-- replace dp_catalog_ctrl_set_pattern() with
dp_catalog_ctrl_set_pattern_state_bit()
Changes
ining until video is
ready")
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index f98df93..245e1b9 100644
--- a/drivers/gpu/
Some of DP link compliant test expects to return fail-safe mode
if prefer detailed timing mode can not be supported by mainlink's
lane and rate after link training. Therefore add fail-safe mode
into connector mode list as backup mode. This patch fixes test
case 4.2.2.1.
Signed-off-by: K
On 1/24/2022 1:04 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-01-24 12:46:10)
Some of DP link compliant test expects to return fail-safe mode
if prefer detailed timing mode can not be supported by mainlink's
lane and rate after link training. Therefore add fail-safe mode
into conn
DP driver is a generic driver which supports both eDP and DP.
For debugging purpose it is required to have capabilities to
differentiate message are generated from eDP or DP. This patch
add connector type into debug messages for this purpose.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm
- add Fixes text string
Fixes: 4b85d405cfe9 ( "drm/msm/dp: reduce link rate if failed at link training
1")
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_panel.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c
b/drivers/gpu/drm/msm/dp/d
On 1/24/2022 5:50 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-01-24 14:44:52)
DP driver is a generic driver which supports both eDP and DP.
For debugging purpose it is required to have capabilities to
differentiate message are generated from eDP or DP. This patch
add connector type
within dp_ctrl.c
3) replace DRM_DEBUG_DP marco with drm_dbg_dp
Changes in V2:
-- replace DRM_DEBUG_DP marco with drm_dbg_dp
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_audio.c | 49 +--
drivers/gpu/drm/msm/dp/dp_catalog.c | 34 ++-
drivers/gpu/drm/msm/dp
-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 16 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 2 +
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 14 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 108 +++--
drivers/gpu
On 1/28/2022 8:59 PM, Dmitry Baryshkov wrote:
Hi,
Thank you for your patch.
On Fri, 28 Jan 2022 at 20:29, Kuogee Hsieh wrote:
Normally, mdp will push one pixel of data per pixel clock to
interface to display. Wide bus feature will increase bus
width from 32 bits to 64 bits so that it can
On 1/28/2022 8:59 PM, Dmitry Baryshkov wrote:
Hi,
Thank you for your patch.
On Fri, 28 Jan 2022 at 20:29, Kuogee Hsieh wrote:
Normally, mdp will push one pixel of data per pixel clock to
interface to display. Wide bus feature will increase bus
width from 32 bits to 64 bits so that it can
into timing configuration by struct msm_dp
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 8 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 2 +
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 14 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
On 2/2/2022 1:56 AM, Dmitry Baryshkov wrote:
On 02/02/2022 03:30, Kuogee Hsieh wrote:
Normally, mdp will push one pixel of data per pixel clock to
interface to display. Wide bus feature will increase bus
width from 32 bits to 64 bits so that it can push two
pixel of data per pixel clock to
On 1/31/2022 6:34 PM, Dmitry Baryshkov wrote:
On 27/01/2022 02:46, Kuogee Hsieh wrote:
DP driver is a generic driver which supports both eDP and DP.
For debugging purpose it is required to have capabilities to
differentiate message are generated from eDP or DP.
This patch do:
1) add connector
On 1/31/2022 6:34 PM, Dmitry Baryshkov wrote:
On 27/01/2022 02:46, Kuogee Hsieh wrote:
DP driver is a generic driver which supports both eDP and DP.
For debugging purpose it is required to have capabilities to
differentiate message are generated from eDP or DP.
This patch do:
1) add connector
1) Add connector_type to debug info to differentiate between eDP and DP
2) add more debug info to cover dp Phy
3) repalce DRM_DEBUG_DP with drm_debug_dp
Kuogee Hsieh (3):
drm/msm/dp: add connector type to enhance debug messages
drm/msm/dp: enhance debug info related to dp phy
drm/msm/dp
patches
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_display.c | 71 ++---
1 file changed, 50 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index 1d7f82e..01371dd 100644
--- a/drivers
DP phy should be initialized and exited symmetrically to avoid
clock being stucked at either on or off error. Add debug info
to cover all DP phy to identify clock issues easily.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 20 ++--
1 file changed, 10
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_audio.c | 49 +++--
drivers/gpu/drm/msm/dp/dp_catalog.c | 34 +++-
drivers/gpu/drm/msm/dp/dp_ctrl.c| 106 +++-
drivers/gpu/drm/msm/dp/dp_display.c | 68
split into 3 patches
1) widebus timing engine programming
2) dsc timing engine
3) enable widebus feature base on chip hardware revision
Kuogee Hsieh (3):
drm/msm/dp: revise timing engine programming to support widebus
feature
drm/msm/dp: revise timing engine programming to support
compression related code from timing
-- remove op_info from struct msm_drm_private
-- remove unnecessary wide_bus_en variables
-- pass wide_bus_en into timing configuration by struct msm_dp
Changes in v3:
-- split patch into 3 patches
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1
Divides horizontal width by 3 at timing engine of interface. There are
major part of compression (DSC) programming have to be done at DSC
controller which is not covered by this patch.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 22
base on chip hardware revision
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +++-
drivers/gpu/drm/msm/dp/dp_catalog.c | 36 +++--
drivers/gpu/drm/msm/dp/dp_catalog.h | 3 ++-
drivers/gpu/drm/msm/dp/dp_ctrl.c
On 2/4/2022 2:05 PM, Dmitry Baryshkov wrote:
On 04/02/2022 21:36, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to
interface.
Timing engine provides driving force for this purpose. This patch base
on HPG (Hardware Programming Guide) to revise timing engine
capability where legacy
chipsets have has_audio_select flag set to true.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 9 ++---
3 files changed, 9 insertions
Hi Stephen,
Are you have more comments?
On 1/24/2022 3:17 PM, Kuogee Hsieh wrote:
Some of DP link compliant test expects to return fail-safe mode
if prefer detailed timing mode can not be supported by mainlink's
lane and rate after link training. Therefore add fail-safe mode
into conn
Hi Stephen,
Can you please review this serial patches.
On 2/2/2022 10:56 AM, Kuogee Hsieh wrote:
1) Add connector_type to debug info to differentiate between eDP and DP
2) add more debug info to cover dp Phy
3) repalce DRM_DEBUG_DP with drm_debug_dp
Kuogee Hsieh (3):
drm/msm/dp: add
On 2/11/2022 3:36 PM, Dmitry Baryshkov wrote:
On Sat, 12 Feb 2022 at 02:23, Kuogee Hsieh wrote:
intf_audio_select() callback function use to configure
HDMI_DP_CORE_SELECT to decide audio output routes to HDMI or DP
interface. HDMI is obsoleted at newer chipset. To keep supporting
legacy hdmi
capability where legacy
chipsets have has_audio_select flag set to true.
Changes in V2:
-- remove has_audio_select flag
-- add BIT(DPU_MDP_AUDIO_SELECT) into dpu_mdp_cfg
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
split into 2 patches
1) widebus timing engine programming
2) enable widebus feature base on chip hardware revision
Kuogee Hsieh (2):
drm/msm/dp: revise timing engine programming to support widebus
feature
drm/msm/dp: enable widebus feature for display port
drivers/gpu/drm/msm/disp/dpu1
-- remove unnecessary wide_bus_en variables
-- pass wide_bus_en into timing configuration by struct msm_dp
Changes in v3:
-- split patch into 3 patches
Changes in v4:
-- rework timing engine to not interfere with dsi/hdmi
-- cover both widebus and compression
Signed-off-by: Kuogee Hsieh
---
drivers
base on chip hardware revision
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +++-
drivers/gpu/drm/msm/dp/dp_catalog.c | 36 +++--
drivers/gpu/drm/msm/dp/dp_catalog.h | 3 ++-
drivers/gpu/drm/msm/dp/dp_ctrl.c
On 2/14/2022 8:22 PM, Bjorn Andersson wrote:
On Mon 14 Feb 16:39 CST 2022, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to interface.
This feature now is required to be enabled to easy migrant to higher
resolution applications in future. However since some
On 2/15/2022 5:34 AM, Dmitry Baryshkov wrote:
On 15/02/2022 01:39, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to
interface.
This feature now is required to be enabled to easy migrant to higher
resolution applications in future. However since some legacy
On 2/15/2022 10:30 AM, Dmitry Baryshkov wrote:
On Tue, 15 Feb 2022 at 20:49, Kuogee Hsieh wrote:
On 2/15/2022 5:34 AM, Dmitry Baryshkov wrote:
On 15/02/2022 01:39, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to
interface.
This feature now is required
revise widebus timing engine programming and enable widebus feature base on chip
hardware revision
Kuogee Hsieh (2):
drm/msm/dpu: revise timing engine programming to support widebus
feature
drm/msm/dp: enable widebus feature for display port
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
timing configuration by struct msm_dp
Changes in v3:
-- split patch into 3 patches
Changes in v4:
-- rework timing engine to not interfere with dsi/hdmi
-- cover both widebus and compression
Changes in v5:
-- remove supports of DSI widebus and compression
Signed-off-by: Kuogee Hsieh
---
drivers
base on chip hardware revision
Changes in v5:
-- DP_INTF_CONFIG_DATABUS_WIDEN
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +++-
drivers/gpu/drm/msm/dp/dp_catalog.c | 34 +++--
drivers/gpu/drm/msm/dp/dp_catalog.h
revise widebus timing engine programming and enable widebus feature base on chip
Kuogee Hsieh (2):
drm/msm/dpu: revise timing engine programming to support widebus
feature
drm/msm/dp: enable widebus feature for display port
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 14
timing configuration by struct msm_dp
Changes in v3:
-- split patch into 3 patches
Changes in v4:
-- rework timing engine to not interfere with dsi/hdmi
-- cover both widebus and compression
Changes in v5:
-- remove supports of DSI widebus and compression
Signed-off-by: Kuogee Hsieh
---
drivers
base on chip hardware revision
Changes in v5:
-- DP_INTF_CONFIG_DATABUS_WIDEN
Changes in v6:
-- fix static inline bool msm_dp_wide_bus_enable() at msm_drv.h
Signed-off-by: Kuogee Hsieh
Reported-by: kernel test robot
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +++-
drivers/gpu/drm/m
On 2/16/2022 9:48 AM, Dmitry Baryshkov wrote:
On Wed, 16 Feb 2022 at 20:34, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to interface.
Timing engine provides driving force for this purpose. This patch base
on HPG (Hardware Programming Guide) to revise
DPTA_HCTL_EN controls data timing which can be different from
video timing. It only required to be enabled either widebus
or compression enabled.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
patches
-- add Tested-by
Signed-off-by: Kuogee Hsieh
Tested-by: Bjorn Andersson
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 10
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 2 +
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 14 ++
drivers/gpu/drm/msm/disp
revise widebus timing engine programming and enable widebus feature base on chip
Kuogee Hsieh (4):
drm/msm/dpu: revise timing engine programming to support widebus
feature
drm/msm/dpu: delete DATA_HCTL_EN from sc7280 hw feature
drm/msm/dpu: replace BIT(x) with correspond marco define
To improve code readability, this patch replace BIT(x) with
correspond register bit define string
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1
base on chip hardware revision
Changes in v5:
-- DP_INTF_CONFIG_DATABUS_WIDEN
Changes in v6:
-- fix Reported-bya issue
-- fix static inline bool msm_dp_wide_bus_enable() at msm_drv.h
Changes in v7:
-- add Tested-by
Signed-off-by: Kuogee Hsieh
Reported-by: kernel test robot
Tested-by: Bjorn Ande
On 2/16/2022 3:46 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-02-02 10:56:39)
Please add some commit text
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_audio.c | 49 +++--
drivers/gpu/drm/msm/dp/dp_catalog.c | 34 +++-
drivers/gpu/drm/msm/dp
DP phy should be initialized and exited symmetrically to avoid
clock being stucked at either on or off error. Add debug info
to cover all DP phy to identify clock issues easily.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 20
Since DRM_DEBUG_DP is deprecated in favor of drm_dbg_dp(NULL, ...),
this patch replace all DRM_DEBUG_DP with drm_dbg_dp().
Changes in v4:
-- replace (strucr drm_dev *)NULL with drm_dev
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_audio.c | 50 ++--
drivers/gpu/drm
patches
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
---
drivers/gpu/drm/msm/dp/dp_display.c | 71 ++---
1 file changed, 50 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index 1d7f82e
Since DRM_DEBUG_DP is deprecated in favor of drm_dbg_dp(NULL, ...),
replace all DRM_DEBUG_DP with drm_dbg_dp().
Kuogee Hsieh (3):
drm/msm/dp: add connector type to enhance debug messages
drm/msm/dp: enhance debug info related to dp phy
drm/msm/dp: replace DRM_DEBUG_DP marco with drm_dbg_dp
On 2/17/2022 11:36 AM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-02-17 10:35:30)
Since DRM_DEBUG_DP is deprecated in favor of drm_dbg_dp(NULL, ...),
this patch replace all DRM_DEBUG_DP with drm_dbg_dp().
Changes in v4:
-- replace (strucr drm_dev *)NULL with drm_dev
Why can'
On 2/16/2022 10:34 PM, Dmitry Baryshkov wrote:
On 17/02/2022 01:05, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to
interface.
Timing engine provides driving force for this purpose. This patch base
on HPG (Hardware Programming Guide) to revise timing
revise widebus timing engine programming and enable widebus feature base on chip
Kuogee Hsieh (4):
drm/msm/dpu: adjust display_v_end for eDP and DP
drm/msm/dpu: replace BIT(x) with correspond marco define string
drm/msm/dpu: revise timing engine programming to support widebus
feature
To improve code readability, this patch replace BIT(x) with
correspond register bit define string
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1
patches
-- add Tested-by
Changes in v8:
-- move new registers writes under DATA_HCTL_EN features check.
Signed-off-by: Kuogee Hsieh
Tested-by: Bjorn Andersson
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 10
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 2 +
.../gpu/drm
: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 116e2b5..284f561 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers
base on chip hardware revision
Changes in v5:
-- DP_INTF_CONFIG_DATABUS_WIDEN
Changes in v6:
-- static inline bool msm_dp_wide_bus_enable() in msm_drv.h
Changes in v7:
-- add Tested-by
Signed-off-by: Kuogee Hsieh
Reported-by: kernel test robot
Tested-by: Bjorn Andersson
---
drivers/gpu/dr
ge support for eDP panels. The panel bridge attaches
to the encoder before the "dp" bridge has a chace to do so. Change
panel_bridge attachment to come after dp_bridge attachment.
Fixes: 8a3b4c17f863 ("drm/msm/dp: employ bridge mechanism for display enable and
disable")
C
⇒ THC63LVD1024 ⇒ DPI panel.
- eDP encoder ⇒ LT8912 ⇒ DSI panel
Signed-off-by: Dmitry Baryshkov
Tested-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_display.c | 2 +-
drivers/gpu/drm/msm/dp/dp_display.h | 2 +-
drivers/gpu/drm/msm/dp/dp_drm.c | 4 ++--
drivers/gpu/drm/msm/dp
On 2/11/2022 2:40 PM, Dmitry Baryshkov wrote:
It is possible to supply display-connector (bridge) to the DP interface,
add support for parsing it too.
Signed-off-by: Dmitry Baryshkov
Tested-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_parser.c | 19 ---
1 file changed
On 2/11/2022 2:40 PM, Dmitry Baryshkov wrote:
There is little point in having both connector and root bridge
implementation in the same driver. Move connector's functionality to the
bridge to let next bridge in chain to override it.
Signed-off-by: Dmitry Baryshkov
This patch break primary (
revise widebus timing engine programming and enable widebus feature base on chip
Kuogee Hsieh (4):
drm/msm/dpu: adjust display_v_end for eDP and DP
drm/msm/dpu: replace BIT(x) with correspond marco define string
drm/msm/dpu: revise timing engine programming to support widebus
feature
: Kuogee Hsieh
Fixes: fc3a69ec68d3 ("drm/msm/dpu: intf timing path for displayport")
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm
patches
-- add Tested-by
Changes in v8:
-- move new registers writes under DATA_HCTL_EN features check.
Signed-off-by: Kuogee Hsieh
Tested-by: Bjorn Andersson
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 10
drivers/gpu/drm/msm/disp/dpu1
To improve code readability, this patch replace BIT(x) with
correspond register bit define string
Signed-off-by: Kuogee Hsieh
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers
DP at sc7280_dp_cfg
Signed-off-by: Kuogee Hsieh
Reported-by: kernel test robot
Tested-by: Bjorn Andersson
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +++-
drivers/gpu/drm/msm/dp/dp_catalog.c | 34 +++--
drivers/gpu/drm/msm/dp/dp_catalog.h | 3 ++-
driver
On 2/18/2022 6:53 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-02-17 13:36:27)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 0d315b4..0c22839 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm
revise widebus timing engine programming and enable widebus feature base on chip
Kuogee Hsieh (4):
drm/msm/dpu: adjust display_v_end for eDP and DP
drm/msm/dpu: replace BIT(x) with correspond marco define string
drm/msm/dpu: revise timing engine programming to support widebus
feature
: Kuogee Hsieh
Fixes: fc3a69ec68d3 ("drm/msm/dpu: intf timing path for displayport")
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Stephen Boyd
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
To improve code readability, this patch replace BIT(x) with
correspond register bit define string
Signed-off-by: Kuogee Hsieh
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Stephen Boyd
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions
uc to avoid passing it as parameter
Signed-off-by: Kuogee Hsieh
Reported-by: kernel test robot
Tested-by: Bjorn Andersson
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +++-
drivers/gpu/drm/msm/dp/dp_catalog.c | 32 -
drivers/gpu/drm/msm/dp/dp_cata
patches
-- add Tested-by
Changes in v8:
-- move new registers writes under DATA_HCTL_EN features check.
Changes in v10:
-- add const inside dpu_encoder_is_widebus_enabled()
-- drop useless parenthesis please
Signed-off-by: Kuogee Hsieh
Tested-by: Bjorn Andersson
Reviewed-by: Dmitry Baryshkov
On 2/18/2022 6:48 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-02-17 13:36:25)
The “DP timing” requires the active region to be defined in the
bottom-right corner of the frame dimensions which is different
with DSI. Therefore both display_h_end and display_v_end need
to be adjusted
On 2/18/2022 6:22 PM, Dmitry Baryshkov wrote:
On Sat, 19 Feb 2022 at 03:55, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2022-02-18 14:32:53)
On 19/02/2022 00:31, Kuogee Hsieh wrote:
On 2/11/2022 2:40 PM, Dmitry Baryshkov wrote:
There is little point in having both connector and root
⇒ THC63LVD1024 ⇒ DPI panel.
- eDP encoder ⇒ LT8912 ⇒ DSI panel
Signed-off-by: Dmitry Baryshkov
---
Tested-by: Kuogee Hsieh
drivers/gpu/drm/msm/dp/dp_display.c | 2 +-
drivers/gpu/drm/msm/dp/dp_display.h | 2 +-
drivers/gpu/drm/msm/dp/dp_drm.c | 4 ++--
drivers/gpu/drm/msm/dp
On 2/23/2022 10:22 AM, Dmitry Baryshkov wrote:
On 23/02/2022 20:21, Kuogee Hsieh wrote:
On 2/18/2022 6:22 PM, Dmitry Baryshkov wrote:
On Sat, 19 Feb 2022 at 03:55, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2022-02-18 14:32:53)
On 19/02/2022 00:31, Kuogee Hsieh wrote:
On 2/11/2022 2
On 2/23/2022 1:33 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-02-23 10:27:26)
On 2/23/2022 10:22 AM, Dmitry Baryshkov wrote:
On 23/02/2022 20:21, Kuogee Hsieh wrote:
In the panel device node.
Can you please share it too?
&soc {
edp_power_supply: edp_p
revise widebus timing engine programming and enable widebus feature base on chip
Kuogee Hsieh (4):
drm/msm/dpu: adjust display_v_end for eDP and DP
drm/msm/dpu: replace BIT(x) with correspond marco define string
drm/msm/dpu: revise timing engine programming to support widebus
feature
: Kuogee Hsieh
Fixes: fc3a69ec68d3 ("drm/msm/dpu: intf timing path for displayport")
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Stephen Boyd
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
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