On DPUs prior to version 4 the VBIF_XINL_QOS_LVL_REMAP_000 register
is at 0x570 offset from vbif base instead of 0x590, due to the
VBIF_XINL_QOS_RP_REMAP_000 having less instances (less possible XINs).
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
disable the feature when
preparing for cmd commit: instead of disabling it when initializing
the command mode, this road was chosen as to open future possibility
of enabling and managing the autorefresh feature in the driver.
Signed-off-by: AngeloGioacchino Del Regno
---
.../drm/msm/disp/dpu1
probably will also be needed
for future SoCs.
Signed-off-by: AngeloGioacchino Del Regno
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 24 +--
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm
DRM_DEV_ERROR should be used across this entire source: convert the
pr_err prints to the first as a cleanup.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm
The number of fractional registers bits is known and already set in
the frac_bits variable of the dsi_pll_config struct here in 10nm:
remove the TODO by simply using that variable.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 4 ++--
1 file changed
tchid number is also used in the a5xx_power.c
function a540_lm_setup to disable the battery current limiter,
which makes faking the Adreno patchid to .2 (which would anyway
be sad) useless and even producing breakages.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/a
The PLL_LOCKDET_RATE_1 was being programmed with a hardcoded value
directly, but the same value was also being specified in the
dsi_pll_regs struct pll_lockdet_rate variable: let's use it!
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 3 ++-
1
Add a function that returns whether the requested CTL is active or not:
this will be used in a later commit to fix command mode panel issues.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 7
play on at least MSM8998.
This patch series fixes the calculation issues and also solves some TODOs
that I've found in this driver.
Tested on:
- Sony Xperia XZ Premium (MSM8998) dual-dsi command-mode LCD display
- F(x)Tec Pro1 (MSM8998) single dsi, video-mode OLED display
AngeloGioacchino Del R
_done function is called: in this case, so,
if the CTL was already running, we can say that the commit is done
if the command transmission is complete (in other terms, if the
interface has been flushed).
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_
prescaler-ON and OFF cases were tested.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 22 +-
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
b/drivers/gpu/drm/msm/dsi/pll
ff-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index c5cf59b
event that we miss one
external TE signal: this will still trigger recovery mechanisms in
case the display is really unreachable.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
di
feature mask and the sblk config for
each DSPP.
Fixes: 4259ff7ae509 ("drm/msm/dpu: add support for pcc color block in dpu
driver")
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 9 +
1 file changed, 5 insertions(+), 4 deletion
Not all DPU versions that are supported in this driver are supposed
to have a 8-Levels VIG QoS setting.
Move this flag to SDM845 and SC7180 specific masks.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++---
1 file changed, 3 insertions
log is not included in this series, as it needs to be cleaned
up a little more) and specifically on:
- Sony Xperia XZ Premium (MSM8998), 4K dual-dsi LCD display, command-mode
- F(x)Tec Pro1 (MSM8998), single-dsi OLED display, video-mode
... And it obviously worked just perfect!
AngeloGioacchino De
em to get the remainder and *then*
call div_u64 to get the division result, as the first is already
giving that result: let's fix it by just caring about the result
of div_u64_rem.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 4 +---
1 file
Il 09/01/21 14:37, AngeloGioacchino Del Regno ha scritto:
In function dpu_encoder_phys_cmd_wait_for_commit_done we are always
checking if the relative CTL is started by waiting for an interrupt
to fire: it is fine to do that, but then sometimes we call this
function while the CTL is up and has
probably will also be needed
for future SoCs.
Signed-off-by: AngeloGioacchino Del Regno
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 24 +--
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm
feature mask and the sblk config for
each DSPP.
Fixes: 4259ff7ae509 ("drm/msm/dpu: add support for pcc color block in dpu
driver")
Signed-off-by: AngeloGioacchino Del Regno
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 19 ---
1 file changed, 12 insertions(+), 7
event that we miss one
external TE signal: this will still trigger recovery mechanisms in
case the display is really unreachable.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
di
Not all DPU versions that are supported in this driver are supposed
to have a 8-Levels VIG QoS setting.
Move this flag to SDM845 and SC7180 specific masks.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++---
1 file changed, 3 insertions
ed patches "drm/msm/dpu: Add a function to retrieve the current CTL
status"
and "drm/msm/dpu: Fix timeout issues on command mode panels" as the
second patch was wrong.
- Fixed patch apply issues on latest linux-next and 5.11-rcX
AngeloGioacchino Del
disable the feature when
preparing for cmd commit: instead of disabling it when initializing
the command mode, this road was chosen as to open future possibility
of enabling and managing the autorefresh feature in the driver.
Signed-off-by: AngeloGioacchino Del Regno
---
.../drm/msm/disp/dpu1
On DPUs prior to version 4 the VBIF_XINL_QOS_LVL_REMAP_000 register
is at 0x570 offset from vbif base instead of 0x590, due to the
VBIF_XINL_QOS_RP_REMAP_000 having less instances (less possible XINs).
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
ff-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 665eb1d
The Adreno 508/509/512 GPUs are stripped versions of the Adreno
5xx found in the mid-end SoCs such as SDM630, SDM636, SDM660 and
SDA variants; these SoCs are usually provided with ZAP firmwares,
but they have no available GPMU.
Signed-off-by: AngeloGioacchino Del Regno
Tested-by: Martin Botka
bad
slownesses after processing the first frame.
Avoiding to execute the RBBM SW Reset before suspend will stop the
lockup issue from happening on at least Adreno 508/509/512.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 8
configuration (including the GPU-specific quirks) and that is
effectively nullifying the efforts.
Let's remove the redundant and wrong write to the PC_DBG_ECO_CNTL
register in order to retain the wanted configuration for the
target GPU.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jordan C
From: Konrad Dybcio
Port over the command from downstream to prevent undefined
behaviour.
Signed-off-by: Konrad Dybcio
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno
(= 2^4) fixes
the issue.
Signed-off-by: Konrad Dybcio
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
From: Konrad Dybcio
Port over the command from downstream to prevent undefined
behaviour.
Signed-off-by: Konrad Dybcio
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/adreno/a5xx.xml.h | 2 ++
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++
2 files changed, 5 insertions
ged emails to reflect new ones
- Tested on F(x)Tec Pro1 and Xperia XZ Premium (MSM8998)
Changes in v2:
- Define REG_A5XX_UCHE_MODE_CNTL and fix open-coded
REG_A5XX_VPC_DBG_ECO_CNTL in the all flat shading optimization
disablement commit, as requested by Rob Clark.
AngeloGioacchino Del Reg
ned-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 81506d2539b0..8c96fc0fc1b7 100644
---
Il 11/01/21 13:04, Sai Prakash Ranjan ha scritto:
A6XX GPUs have support for last level cache(LLC) also known
as system cache and need to set the bus attributes to
use it. Currently we use a generic adreno iommu address space
implementation which are also used by older GPU generations
which do no
Il 31/01/21 20:50, Rob Clark ha scritto:
On Sat, Jan 9, 2021 at 5:51 AM AngeloGioacchino Del Regno
wrote:
The VCO rate was being miscalculated due to a big overlook during
the process of porting this driver from downstream to upstream:
here we are really recalculating the rate of the VCO by
Il 01/02/21 18:31, Rob Clark ha scritto:
On Mon, Feb 1, 2021 at 9:18 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 9:05 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 7:47 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 2:11 AM AngeloGioacchino Del Regno
wrote:
Il 31/01/21 20:50, Rob Clark ha
Il 02/02/21 19:45, Rob Clark ha scritto:
On Tue, Feb 2, 2021 at 6:32 AM AngeloGioacchino Del Regno
wrote:
Il 01/02/21 18:31, Rob Clark ha scritto:
On Mon, Feb 1, 2021 at 9:18 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 9:05 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 7:47 AM Rob Clark
ng in the MDP and the block really needs
recovery, this "trick" won't save anyone and the recovery will anyway be
triggered, as the PP-done will anyway timeout.
Suggested-by: AngeloGioacchino Del Regno
Signed-off-by: Marijn Suijten
Reviewed-by: AngeloGioacchino Del Regno
---
Il gio 8 apr 2021, 21:05 Rob Clark ha scritto:
> On Wed, Apr 7, 2021 at 12:11 PM AngeloGioacchino Del Regno
> wrote:
> >
> > Il 07/04/21 20:19, abhin...@codeaurora.org ha scritto:
> > > Hi Marijn
> > >
> > > On 2021-04-06 14:47, Marijn Suijten wro
k_bit = 0x3, /* TODO: 2 for LP_DDR4 */
.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
OK on Xperia 5 II (SM8250)
Reviewed-by: AngeloGioacchino Del Regno
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
Add a function that returns whether the requested CTL is active or not:
this will be used in a later commit to fix command mode panel issues.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 7
_done function is called: in this case, so,
if the CTL was already running, we can say that the commit is done
if the command transmission is complete (in other terms, if the
interface has been flushed).
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_
The enum dpu_clk_ctrl_type misses DPU_CLK_CTRL_DMA{2,3} even though
this driver does actually handle both, if present: add the two in
preparation for adding support for SoCs having them.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
1 file
Bringup functionality for MSM8998 in the DPU, driver which is mostly
the same as SDM845 (just a few variations).
Signed-off-by: AngeloGioacchino Del Regno
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 335 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers
Add yaml binding for msm8998 dpu1 support.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/display/msm/dpu-msm8998.yaml | 220 ++
1 file changed, 220 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml
diff --git a
#x27;bi_tcxo' as ref clock of the DSI
PHYs")
Signed-off-by: Marijn Suijten
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 4 +++-
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 +++-
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
e.org/
and prevented the removal of "xo" at that time.
Signed-off-by: Marijn Suijten
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/clk/qcom/gcc-sdm660.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/g
Il 09/09/21 15:46, Dmitry Baryshkov ha scritto:
On 08/09/2021 17:22, Jeffrey Hugo wrote:
On Wed, Sep 8, 2021 at 2:26 AM Dmitry Baryshkov
wrote:
Hi,
On Tue, 7 Sept 2021 at 22:13, Jeffrey Hugo wrote:
On Wed, Sep 1, 2021 at 12:11 PM AngeloGioacchino Del Regno
wrote:
Bringup functionality
Il 10/09/21 23:48, Marijn Suijten ha scritto:
Hi Angelo!
On 2021-09-01 19:43:47, AngeloGioacchino Del Regno wrote:
In function dpu_encoder_phys_cmd_wait_for_commit_done we are always
checking if the relative CTL is started by waiting for an interrupt
to fire: it is fine to do that, but then
Add a function that returns whether the requested CTL is active or not:
this will be used in a later commit to fix command mode panel issues.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 7
_done function is called: in this case, so,
if the CTL was already running, we can say that the commit is done
if the command transmission is complete (in other terms, if the
interface has been flushed).
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_
_10nm: Fix dividing the same numbers
twice").
Signed-off-by: Marijn Suijten
---
Changes in v2:
- Corrected two typos in the first commit-message sentence.
Reviewed-By: AngeloGioacchino Del Regno
eck if the devfreq
instance is not NULL before proceeding.
Fixes: 658f4c829688 ("drm/msm/devfreq: Add 1ms delay before clamping freq")
Reviewed-by: Konrad Dybcio
Signed-off-by: Marijn Suijten
Reviewed-by: AngeloGioacchino Del Regno
e the
devm variant of kzalloc().
Fixes: 8f59ee9a570c ("drm/msm/dsi: Adjust probe order")
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/msm_drv.c | 81 ---
1 file changed, 38 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu
Il 25/11/21 12:53, Dmitry Baryshkov ha scritto:
On 07/09/2021 21:37, Rob Herring wrote:
On Wed, Sep 01, 2021 at 08:11:38PM +0200, AngeloGioacchino Del Regno wrote:
Add yaml binding for msm8998 dpu1 support.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/display/msm/dpu
Il 26/11/21 01:06, Dmitry Baryshkov ha scritto:
On 25/11/2021 18:09, AngeloGioacchino Del Regno wrote:
Since commit 8f59ee9a570c ("drm/msm/dsi: Adjust probe order"), the
DSI host gets initialized earlier, but this caused unability to probe
the entire stack of components because they
Il 26/11/21 01:06, Dmitry Baryshkov ha scritto:
On 25/11/2021 18:09, AngeloGioacchino Del Regno wrote:
Since commit 8f59ee9a570c ("drm/msm/dsi: Adjust probe order"), the
DSI host gets initialized earlier, but this caused unability to probe
the entire stack of components because they
Il 29/11/21 03:20, Dmitry Baryshkov ha scritto:
Hi,
On 25/11/2021 18:09, AngeloGioacchino Del Regno wrote:
Since commit 8f59ee9a570c ("drm/msm/dsi: Adjust probe order"), the
DSI host gets initialized earlier, but this caused unability to probe
the entire stack of components becaus
Il 29/11/21 15:53, Dmitry Baryshkov ha scritto:
Hi,
On Mon, 29 Nov 2021 at 17:15, AngeloGioacchino Del Regno
wrote:
Il 29/11/21 03:20, Dmitry Baryshkov ha scritto:
Hi,
On 25/11/2021 18:09, AngeloGioacchino Del Regno wrote:
Since commit 8f59ee9a570c ("drm/msm/dsi: Adjust probe order&q
osed to.
Instead of actually fixing that patch, I went for "simplifying" the
approach by not initializing the entire MDSS, but just the interrupt
controller, which still untangles the infinite probe deferrals, but
actually doesn't even touch most of the already present logic in place.
An
fying some bind/unbind functions around drm/msm,
as some of them are using drm_device just to grab a pointer to the
msm_drm_private structure, which we now retrieve in one call.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 16 +++-
drivers/gpu/dr
domain is registered everytime we call bind() on msm_pdev, add
a new *remove function pointer to msm_mdss_funcs, used to remove the
irq domain only at msm_pdev_remove() time.
Fixes: 8f59ee9a570c ("drm/msm/dsi: Adjust probe order")
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/g
Il 30/11/21 15:10, AngeloGioacchino Del Regno ha scritto:
Context, from patch 2/2:
Since commit 8f59ee9a570c ("drm/msm/dsi: Adjust probe order"), the
DSI host gets initialized earlier, but this caused unability to probe
the entire stack of components because they all depend on interru
27;t even touch most of the already present logic in place.
AngeloGioacchino Del Regno (2):
drm/msm: Allocate msm_drm_private early and pass it as driver data
drm/msm: Initialize MDSS irq domain at probe time
drivers/gpu/drm/msm/adreno/adreno_device.c | 16 ++---
drivers/gpu/drm/msm/disp/dpu
domain is registered everytime we call bind() on msm_pdev, add
a new *remove function pointer to msm_mdss_funcs, used to remove the
irq domain only at msm_pdev_remove() time.
Fixes: 8f59ee9a570c ("drm/msm/dsi: Adjust probe order")
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/g
fying some bind/unbind functions around drm/msm,
as some of them are using drm_device just to grab a pointer to the
msm_drm_private structure, which we now retrieve in one call.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 16 +++-
drivers/gpu/dr
("drm/msm/dsi: Adjust probe order")
Co-Developed-By: AngeloGioacchino Del Regno
Signed-off-by: Dmitry Baryshkov
---
When checking your patch, I noticed that IRQ domain is created before
respective MDSS clocks are enabled. This does not look like causing any
issues at this time, but it d
Il 03/12/21 14:14, Dmitry Baryshkov ha scritto:
On 03/12/2021 13:43, AngeloGioacchino Del Regno wrote:
Il 01/12/21 21:20, Dmitry Baryshkov ha scritto:
Since commit 8f59ee9a570c ("drm/msm/dsi: Adjust probe order"), the
DSI host gets initialized earlier, but this caused unability to
Il 02/10/21 00:33, Dmitry Baryshkov ha scritto:
On 11/09/2021 19:39, AngeloGioacchino Del Regno wrote:
In function dpu_encoder_phys_cmd_wait_for_commit_done we are always
checking if the relative CTL is started by waiting for an interrupt
to fire: it is fine to do that, but then sometimes we
Il 11/12/21 22:57, Marijn Suijten ha scritto:
On 2021-12-12 00:49:09, Dmitry Baryshkov wrote:
On Sun, 12 Dec 2021 at 00:35, Marijn Suijten
wrote:
[..]
On this note, does it perhaps make more sense to call the "internal"
_dpu_encoder_phys_cmd_wait_for_idle function directly, instead of going
th
ively we could just return -EBUSY in this case, but that has the
disadvantage of causing system suspend to fail.
Signed-off-by: Rob Clark
Reviewed-by: AngeloGioacchino Del Regno
Il 02/03/22 18:27, Akhil P Oommen ha scritto:
Retry infinitely on resume failure because there is nothing much we can
do if GPU is not ON. Also, this helps us to avoid checking for the
return value of pm_runtime_get() to see if GPU is ON.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm
Il 11/03/22 00:46, Rob Clark ha scritto:
From: Rob Clark
Hey Rob,
looks like you've somehow lost the commit description on this one!
Cheers,
Angelo
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Il giorno lun 23 set 2019 alle ore 02:45 Jeffrey Hugo
ha scritto:
>
> On Sun, Sep 22, 2019 at 8:16 AM wrote:
> >
> > From: "Angelo G. Del Regno"
> >
> > Some SoCs, like MSM8956/8976 (and APQ variants), do feature these
> > clocks and we need to enable them in order to get the hardware to
> > pro
Il giorno lun 23 set 2019 alle ore 18:37 Rob Clark
ha scritto:
>
> On Sat, Sep 21, 2019 at 3:04 AM wrote:
> >
> > From: "Angelo G. Del Regno"
> >
> > The Adreno 510 GPU is a stripped version of the Adreno 5xx,
> > found in low-end SoCs like 8x56 and 8x76, which has 256K of
> > GMEM, with no GPMU
Il giorno lun 23 set 2019 alle ore 20:23 Rob Clark
ha scritto:
>
> On Mon, Sep 23, 2019 at 10:27 AM AngeloGioacchino Del Regno
> wrote:
> >
> > Il giorno lun 23 set 2019 alle ore 18:37 Rob Clark
> > ha scritto:
> > >
> > > On Sat, Sep 21, 2019 at 3:
log2 and
some others with the "real" number of registers.
Hardware magic register layouts, maybe :)))
-- Angelo
> > Signed-off-by: Konrad Dybcio
> > Signed-off-by: AngeloGioacchino Del Regno
> > ---
> > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +-
> > 1
Il 19/07/23 23:54, Marijn Suijten ha scritto:
On 2023-07-19 01:02:56, Dmitry Baryshkov wrote:
On 19/07/2023 00:24, Marijn Suijten wrote:
This node has always resided in the wrong spot, making it somewhat
harder to contribute new node entries while maintaining proper sorting
around it. Move the
;heap_rss_size);
return bo->base.base.size;
}
return 0;
}
Apart from that,
Reviewed-by: AngeloGioacchino Del Regno
on
Reviewed-by: Steven Price
Reviewed-by: AngeloGioacchino Del Regno
res = 0;
The initialization of `res` is redundant...
enum drm_gem_object_status res;
res = (bo->base.madv == PANFROST_MADV_DONTNEED) ? DRM_GEM_OBJECT_PURGEABLE : 0;
P.S.: 88 columns are generally fine, so this could also fit in one line.
After that,
Reviewed-by: AngeloGioacchino Del Regno
: AngeloGioacchino Del Regno
.
engine keystrings and Panfrost-specific drm-curfreq- pairs.
Signed-off-by: Adrián Larumbe
Reviewed-by: Boris Brezillon
Reviewed-by: Steven Price
Nitpick apart:
Reviewed-by: AngeloGioacchino Del Regno
Il 22/04/22 10:52, cgel@gmail.com ha scritto:
From: Lv Ruyi
The irq_of_parse_and_map() function returns 0 on failure, and does not
return an negative value.
Reported-by: Zeal Robot
Signed-off-by: Lv Ruyi
Reviewed-by: AngeloGioacchino Del Regno
Anderson
Acked-by: Jyri Sarha
Tested-by: Jyri Sarha
For MediaTek mtk_drm_drv:
Tested-by: AngeloGioacchino Del Regno
Il 30/05/23 13:44, Dmitry Baryshkov ha scritto:
On Tue, 30 May 2023 at 10:24, Neil Armstrong wrote:
Hi Marijn, Dmitry, Caleb, Jessica,
On 29/05/2023 23:11, Marijn Suijten wrote:
On 2023-05-22 04:16:20, Dmitry Baryshkov wrote:
+ if (ctx->dsi->dsc) {
dsi->dsc is always set, thus this con
Il 30/05/23 17:44, Neil Armstrong ha scritto:
On 30/05/2023 14:36, Dmitry Baryshkov wrote:
On 30/05/2023 15:15, AngeloGioacchino Del Regno wrote:
Il 30/05/23 13:44, Dmitry Baryshkov ha scritto:
On Tue, 30 May 2023 at 10:24, Neil Armstrong wrote:
Hi Marijn, Dmitry, Caleb, Jessica,
On 29/05
nts during reviews of
new patches built on existing code.
Signed-off-by: Krzysztof Kozlowski
For MediaTek
Reviewed-by: AngeloGioacchino Del Regno
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