On 10/16/2020 3:49 AM, Matthias Kaehlcke wrote:
Hi,
On Thu, Oct 15, 2020 at 12:07:01AM +0530, man...@codeaurora.org wrote:
On 2020-10-14 18:59, Akhil P Oommen wrote:
On 10/9/2020 10:27 PM, Matthias Kaehlcke wrote:
On Fri, Oct 09, 2020 at 08:05:10AM -0700, Doug Anderson wrote:
Hi,
On Thu
Add cooling device support to gpu. A cooling device is bound to a
thermal zone to allow thermal mitigation.
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings
Register GPU as a devfreq cooling device so that it can be passively
cooled by the thermal framework.
Signed-off-by: Akhil P Oommen
---
Changes in v2:
1. Update the dt bindings documentation
drivers/gpu/drm/msm/msm_gpu.c | 12
drivers/gpu/drm/msm/msm_gpu.h | 2 ++
2 files
Add cooling-cells property and the cooling maps for the gpu tzones
to support GPU cooling.
Signed-off-by: Akhil P Oommen
---
The thermal policy should be set as 'step_wise' for gpu tzones from
the userspace during boot up.
arch/arm64/boot/dts/qcom/sc7180
of_icc_get() to target specific code where it is
required.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 21 +++--
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 20 ++--
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 29
Implement the shutdown callback for adreno gpu platform device
to safely shutdown it before a system reboot. This helps to avoid
futher transactions from gpu after the smmu is moved to bypass mode.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 6 ++
1 file
On 10/19/2020 8:29 PM, Jordan Crouse wrote:
On Mon, Oct 19, 2020 at 06:49:18PM +0530, Akhil P Oommen wrote:
On targets with a6xx gpu, there is a duplicate gpu icc node listed in
the interconnect summary. On these targets, calling
This first sentence is confusing to me. I think the following
On Mon, May 29, 2023 at 03:52:32PM +0200, Konrad Dybcio wrote:
>
> A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It
> features no GMU, as it's implemented solely on SoCs with SMD_RPM.
> What's more interesting is that it does not feature a VDDGX line
> either, being powered sole
A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30)
> | 0x3f);
> + else if (adreno_is_a610(adreno_gpu))
> gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30)
> | 0x3ffff);
> else
> gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30)
> | 0x1f);
Reviewed-by: Akhil P Oommen
-Akhil
>
> --
> 2.40.1
>
On Mon, May 29, 2023 at 03:52:34PM +0200, Konrad Dybcio wrote:
>
> The GPU can only be one at a time. Turn a series of ifs into if +
> elseifs to save some CPU cycles.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Konrad Dybcio
Reviewed-by: Akhil P Oommen
-Akhil
&g
plicit revision matching. Do so to allow differentiating
> between A619 and A619_holi.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Konrad Dybcio
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +-
> drivers/
fuse values with
> of_machine_is_compatible(). Do just that to enable frequency limiting
> on these SoCs.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Konrad Dybcio
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 +++
UINT_MAX;
> +}
> +
> static u32 a618_get_speed_bin(u32 fuse)
> {
> if (fuse == 0)
> @@ -2195,6 +2219,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct
> adreno_gpu *adreno_gpu, u3
> {
> u32 val = UINT_MAX;
>
> + if (adreno_is_a610(a
On Thu, Jun 15, 2023 at 12:34:06PM +0200, Konrad Dybcio wrote:
>
> On 6.06.2023 19:18, Akhil P Oommen wrote:
> > On Mon, May 29, 2023 at 03:52:26PM +0200, Konrad Dybcio wrote:
> >>
> >> Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wra
On Thu, Jun 15, 2023 at 10:59:23PM +0200, Konrad Dybcio wrote:
>
> On 15.06.2023 22:11, Akhil P Oommen wrote:
> > On Thu, Jun 15, 2023 at 12:34:06PM +0200, Konrad Dybcio wrote:
> >>
> >> On 6.06.2023 19:18, Akhil P Oommen wrote:
> >>> On Mon, May 29, 202
On Fri, Jun 16, 2023 at 02:28:15PM +0200, Juerg Haefliger wrote:
>
> Add missing MODULE_FIRMWARE macros and remove some for firmwares that
> the driver no longer references.
>
> Signed-off-by: Juerg Haefliger
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 23 ++
> 1 fi
On Thu, Jun 15, 2023 at 11:43:04PM +0200, Konrad Dybcio wrote:
>
> On 10.06.2023 00:06, Akhil P Oommen wrote:
> > On Mon, May 29, 2023 at 03:52:29PM +0200, Konrad Dybcio wrote:
> >>
> >> Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
> >
On Sat, Jun 17, 2023 at 02:00:50AM +0200, Konrad Dybcio wrote:
>
> On 16.06.2023 19:54, Akhil P Oommen wrote:
> > On Thu, Jun 15, 2023 at 11:43:04PM +0200, Konrad Dybcio wrote:
> >>
> >> On 10.06.2023 00:06, Akhil P Oommen wrote:
> >>> On Mon, May 29, 202
On Fri, Jul 07, 2023 at 08:27:18PM +0300, Dmitry Baryshkov wrote:
>
> On 07/07/2023 18:03, Jordan Crouse wrote:
> > On Thu, Jul 06, 2023 at 09:55:13PM +0300, Dmitry Baryshkov wrote:
> > >
> > > On 10/03/2023 00:20, Jordan Crouse wrote:
> > > > While booting with amd,imageon on a headless target t
6XX_SP_LB_5_DATA, 0x200),
> - SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x2000),
> + SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x800),
> SHADER(A6XX_SP_CB_LEGACY_DATA, 0x280),
> SHADER(A6XX_SP_UAV_DATA, 0x80),
> SHADER(A6XX_SP_INST_TAG, 0x80),
> --
> 2.41.0
>
Reviewed-by: Akhil P Oommen
-Akhil
x27;ve already mapped it once in
>* submit_reloc()
>*/
> - if (WARN_ON(!ptr))
> + if (WARN_ON(IS_ERR(ptr)))
nit: can we make this IS_ERR_OR_NULL() check to retain the current
validation? A null is catastrophic here. Yeah, I see that the current
On Fri, Jun 30, 2023 at 09:20:43AM -0700, Rob Clark wrote:
>
> From: Rob Clark
>
> The range is actually len+1.
>
> Signed-off-by: Rob Clark
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++--
> 1 file changed, 2
On Fri, Jul 07, 2023 at 01:22:56AM +0200, Konrad Dybcio wrote:
>
> On 6.07.2023 23:10, Rob Clark wrote:
> > From: Rob Clark
> >
> > Even in the ocmem case, the allocated ocmem buffer size should match the
> > requested size.
> >
> > Signed-off-by: Rob Clark
> > ---
> [...]
>
> > +
> > + WAR
On Thu, Jul 06, 2023 at 02:10:38PM -0700, Rob Clark wrote:
>
> From: Rob Clark
>
> It is better to explicitly list it. With the move to opaque chip-id's
> for future devices, we should avoid trying to infer things like
> generation from the numerical value.
>
> Signed-off-by: Rob Clark
> ---
On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
>
> On 07/07/2023 00:10, Rob Clark wrote:
> > From: Rob Clark
> >
> > There are cases where there are differences due to SoC integration.
> > Such as cache-coherency support, and (in the next patch) e-fuse to
> > speedbin mappings
On Fri, Jul 07, 2023 at 06:45:42AM +0300, Dmitry Baryshkov wrote:
>
> On 07/07/2023 00:10, Rob Clark wrote:
> > From: Rob Clark
> >
> > Since the revision becomes an opaque identifier with future GPUs, move
> > away from treating different ranges of bits as having a given meaning.
> > This means
On Fri, Jul 07, 2023 at 02:40:47AM +0200, Konrad Dybcio wrote:
>
> On 6.07.2023 23:10, Rob Clark wrote:
> > From: Rob Clark
> >
> > There are cases where there are differences due to SoC integration.
> > Such as cache-coherency support, and (in the next patch) e-fuse to
> > speedbin mappings.
>
On Thu, Jul 13, 2023 at 03:25:33PM -0700, Rob Clark wrote:
>
> On Thu, Jul 13, 2023 at 1:06 PM Akhil P Oommen
> wrote:
> >
> > On Thu, Jul 06, 2023 at 02:10:38PM -0700, Rob Clark wrote:
> > >
> > > From: Rob Clark
> > >
> > > It is be
On Thu, Jul 13, 2023 at 03:06:36PM -0700, Rob Clark wrote:
>
> On Thu, Jul 13, 2023 at 2:39 PM Akhil P Oommen
> wrote:
> >
> > On Fri, Jul 07, 2023 at 06:45:42AM +0300, Dmitry Baryshkov wrote:
> > >
> > > On 07/07/2023 00:10, Rob Clark wrote:
> > &
in code does just that (AND returns an
> invalid error, (int)UINT_MAX). Fix that by defaulting to speedbin 0
> (which is conveniently always bound to fuseval == 0).
Wish we documented somewhere that we should reserve BIT(0) for fuse
val=0 always and assume that would be the super SKU.
Reviewed
On Tue, Sep 26, 2023 at 08:24:37PM +0200, Konrad Dybcio wrote:
>
> Some (many?) devices with A635 expect a ZAP shader to be loaded.
>
> Set the file name to allow for that.
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
> 1 file changed, 1 insertion(
On Tue, Sep 26, 2023 at 08:24:40PM +0200, Konrad Dybcio wrote:
>
> GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute).
> On platforms that support it (in firmware), it is necessary to
> describe that link, or Adreno register access will hang the board.
>
> Add that and fix up th
On Tue, Sep 26, 2023 at 08:24:41PM +0200, Konrad Dybcio wrote:
>
> The SMMUs on sc7280 are cache-coherent. APPS_SMMU is marked as such,
> mark the GPU one as well.
>
> Signed-off-by: Konrad Dybcio
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> arch/arm64/boot/dts/qcom/s
On Tue, Oct 17, 2023 at 12:33:45AM -0700, Rob Clark wrote:
>
> On Mon, Oct 16, 2023 at 1:12 PM Akhil P Oommen
> wrote:
> >
> > On Tue, Sep 26, 2023 at 08:24:37PM +0200, Konrad Dybcio wrote:
> > >
> > > Some (many?) devices with A635 expect a ZAP shader
On Tue, Oct 17, 2023 at 01:22:27AM +0530, Akhil P Oommen wrote:
>
> On Tue, Sep 26, 2023 at 08:24:36PM +0200, Konrad Dybcio wrote:
> >
> > When opp-supported-hw is present under an OPP node, but no form of
> > opp_set_supported_hw() has been called, that OPP is ignored b
Add a new sku to the fuse map of 7c3 gpu.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 841e47a..61bb21d 100644
--- a/drivers/gpu
Add support for a new sc7280 sku in the gpu's opp table.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index d7
Add a new sku to the fuse map of 7c3 gpu.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 841e47a..61bb21d
Add support for a new sc7280 sku in the gpu's opp table.
Signed-off-by: Akhil P Oommen
---
Changes in v2:
- Commit message update
arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/
BUG_ON(!node);
ret = a6xx_gmu_init(a6xx_gpu, node);
+ of_node_put(node);
if (ret) {
a6xx_destroy(&(a6xx_gpu->base.base));
return ERR_PTR(ret);
Reviewed-by: Akhil P Oommen
-Akhil.
On 6/8/2022 3:00 AM, Rob Clark wrote:
On Tue, Sep 28, 2021 at 7:52 AM Akhil P Oommen wrote:
On 9/27/2021 8:59 PM, Rob Clark wrote:
From: Rob Clark
I've seen a few crashes like:
Internal error: synchronous external abort: 9610 [#1] PREEMPT SMP
Modules link
On 6/9/2022 2:17 AM, Rob Clark wrote:
On Wed, Jun 8, 2022 at 12:36 PM Akhil P Oommen wrote:
On 6/8/2022 3:00 AM, Rob Clark wrote:
On Tue, Sep 28, 2021 at 7:52 AM Akhil P Oommen wrote:
On 9/27/2021 8:59 PM, Rob Clark wrote:
From: Rob Clark
I've seen a few crashes like:
Int
On 6/9/2022 8:03 PM, Douglas Anderson wrote:
>From testing on sc7180-trogdor devices, reading the GMU registers
">" ??
needs the GMU clocks to be enabled. Those clocks get turned on in
a6xx_gmu_resume(). Confusingly enough, that function is called as a
result of the runtime_pm of the GPU "stru
On 6/9/2022 8:27 PM, Doug Anderson wrote:
Hi,
On Thu, Jun 9, 2022 at 7:16 AM Akhil P Oommen wrote:
On 6/9/2022 2:17 AM, Rob Clark wrote:
On Wed, Jun 8, 2022 at 12:36 PM Akhil P Oommen wrote:
On 6/8/2022 3:00 AM, Rob Clark wrote:
On Tue, Sep 28, 2021 at 7:52 AM Akhil P Oommen wrote:
On 9
ruct
msm_ringbuffer *ring,
msm_devfreq_idle(gpu);
mutex_unlock(&gpu->active_lock);
+ pm_runtime_put_autosuspend(&gpu->pdev->dev);
+
msm_gem_submit_put(submit);
}
Reviewed-by: Akhil P Oommen
-Akhil.
On 6/9/2022 9:24 PM, Rob Clark wrote:
On Thu, Jun 9, 2022 at 7:34 AM Douglas Anderson wrote:
From testing on sc7180-trogdor devices, reading the GMU registers
needs the GMU clocks to be enabled. Those clocks get turned on in
a6xx_gmu_resume(). Confusingly enough, that function is called as a
r
On 6/9/2022 10:17 PM, Douglas Anderson wrote:
>From testing on sc7180-trogdor devices, reading the GMU registers
needs the GMU clocks to be enabled. Those clocks get turned on in
a6xx_gmu_resume(). Confusingly enough, that function is called as a
result of the runtime_pm of the GPU "struct device
On 6/9/2022 11:42 PM, Rob Clark wrote:
On Thu, Jun 9, 2022 at 11:04 AM Akhil P Oommen wrote:
On 6/9/2022 10:17 PM, Douglas Anderson wrote:
>From testing on sc7180-trogdor devices, reading the GMU registers
needs the GMU clocks to be enabled. Those clocks get turned on in
a6xx_gmu_res
ncs->gpu_busy(gpu, &sample_rate);
df->time = ktime_get();
+ df->suspended = false;
+ mutex_unlock(&df->lock);
devfreq_resume_device(df->devfreq);
}
@@ -261,6 +280,10 @@ void msm_devfreq_suspend(struct msm_gpu *gpu)
if (!has_devfreq(gpu))
return;
+ mutex_lock(&df->lock);
+ df->suspended = true;
+ mutex_unlock(&df->lock);
+
devfreq_suspend_device(df->devfreq);
cancel_idle_work(df);
nit: in the commit subject: 6xx -> a6xx
Reviewed-by: Akhil P Oommen
-Akhil.
On 6/29/2022 9:59 AM, Bjorn Andersson wrote:
On Tue 10 May 02:53 CDT 2022, Akhil P Oommen wrote:
Add a new sku to the fuse map of 7c3 gpu.
Signed-off-by: Akhil P Oommen
Is this series still needed/wanted? I've been waiting for patch 1 to be
merged in the driver so that I can pick up th
ct adreno_gpu *gpu)
{
return gpu->revn == 630;
@@ -268,6 +273,12 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu)
return gpu->revn == 660;
}
+/* check for a615, a616, a618, a619 or any derivatives */
+static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
+{
+ return gpu->revn == 615 || gpu->revn == 616 || gpu->revn == 618 ||
gpu->revn == 619;
+}
+
static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
{
return adreno_is_a660(gpu) || adreno_is_7c3(gpu);
Minor nits, but any way "Reviewed-by: Akhil P Oommen
"
-Akhil
)
goto err_memory;
} else {
- BUG_ON(adreno_is_a660_family(adreno_gpu));
-
/* HFI v1, has sptprac */
gmu->legacy = true;
Reviewed-by: Akhil P Oommen
-Akhil
))
val = adreno_7c3_get_speed_bin(fuse);
Reviewed-by: Akhil P Oommen
-Akhil
struct adreno_gpu *gpu)
{
- return gpu->revn == 618;
+ return gpu->revn == 618;
}
etc...
Reviewed-by: Akhil P Oommen
-Akhil.
ic improvements.
Akhil P Oommen (7):
drm/msm: Remove unnecessary pm_runtime_get/put
drm/msm: Correct pm_runtime votes in recover worker
drm/msm: Fix cx collapse issue during recovery
drm/msm: Ensure cx gdsc collapse during recovery
arm64: dts: qcom: sc7280: Update gpu register list
drm/msm/a6
We already enable gpu power from msm_gpu_submit(), so avoid a duplicate
pm_runtime_get/put from msm_job_run().
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/msm_ringbuffer.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c
b/drivers/gpu/drm
In the scenario where there is one a single submit which is hung, gpu is
power collapsed when it is retired. Because of this, by the time we call
reover(), gpu state would be already clear. Fix this by correctly
managing the pm runtime votes.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm
n gpu and its
smmu. So the *struct gpu device* needs to be runtime suspended to ensure
that the iommu driver removes its vote on cx gdsc.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++--
drivers/gpu/drm/msm/msm_gpu.c | 2 --
2 files change
-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 13 -
drivers/gpu/drm/msm/msm_gpu.c | 4
drivers/gpu/drm/msm/msm_gpu.h | 1 +
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu
Update gpu register array with gpucc memory region.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e66fc67
When prepare-slumber hfi fails, we should follow a6xx_gmu_force_off()
sequence.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno
We can do a few more things to improve our chance at a successful gpu
recovery, especially during a hangcheck timeout:
1. Halt CP and GMU core
2. Do RBBM GBIF HALT sequence
3. Do a soft reset of GPU core
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 4 ++
drivers
On 7/7/2022 10:40 PM, Rob Clark wrote:
On Thu, Jul 7, 2022 at 9:11 AM Akhil P Oommen wrote:
There are some hardware logic under CX domain. For a successful
recovery, we should ensure cx headswitch collapses to ensure all the
stale states are cleard out. This is especially true to for a6xx
ts.
Changes in v2:
- Rebased on msm-next tip
Akhil P Oommen (7):
drm/msm: Remove unnecessary pm_runtime_get/put
drm/msm: Correct pm_runtime votes in recover worker
drm/msm: Fix cx collapse issue during recovery
drm/msm: Ensure cx gdsc collapse during recovery
arm64: dts: qcom: sc7
We already enable gpu power from msm_gpu_submit(), so avoid a duplicate
pm_runtime_get/put from msm_job_run().
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/msm_ringbuffer.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/msm
In the scenario where there is one a single submit which is hung, gpu is
power collapsed when it is retired. Because of this, by the time we call
reover(), gpu state would be already clear. Fix this by correctly
managing the pm runtime votes.
Signed-off-by: Akhil P Oommen
---
(no changes since
n gpu and its
smmu. So the *struct gpu device* needs to be runtime suspended to ensure
that the iommu driver removes its vote on cx gdsc.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++--
drivers/gpu/drm/msm/msm_gpu.c
-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 13 -
drivers/gpu/drm/msm/msm_gpu.c | 4
drivers/gpu/drm/msm/msm_gpu.h | 1 +
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno
Update gpu register array with gpucc memory region.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280
We can do a few more things to improve our chance at a successful gpu
recovery, especially during a hangcheck timeout:
1. Halt CP and GMU core
2. Do RBBM GBIF HALT sequence
3. Do a soft reset of GPU core
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno
When prepare-slumber hfi fails, we should follow a6xx_gmu_force_off()
sequence.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b
On 7/12/2022 4:52 AM, Doug Anderson wrote:
Hi,
On Fri, Jul 8, 2022 at 11:00 PM Akhil P Oommen wrote:
There are some hardware logic under CX domain. For a successful
recovery, we should ensure cx headswitch collapses to ensure all the
stale states are cleard out. This is especially true to for
On 7/12/2022 10:14 PM, Rob Clark wrote:
On Mon, Jul 11, 2022 at 10:05 PM Akhil P Oommen
wrote:
On 7/12/2022 4:52 AM, Doug Anderson wrote:
Hi,
On Fri, Jul 8, 2022 at 11:00 PM Akhil P Oommen wrote:
There are some hardware logic under CX domain. For a successful
recovery, we should ensure cx
On 7/12/2022 4:57 AM, Doug Anderson wrote:
Hi,
On Fri, Jul 8, 2022 at 11:00 PM Akhil P Oommen wrote:
Update gpu register array with gpucc memory region.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 --
1 file changed, 4 insertions
On 7/14/2022 11:10 AM, Akhil P Oommen wrote:
On 7/12/2022 4:57 AM, Doug Anderson wrote:
Hi,
On Fri, Jul 8, 2022 at 11:00 PM Akhil P Oommen
wrote:
Update gpu register array with gpucc memory region.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
arch/arm64/boot/dts/qcom/sc7280
On 7/19/2022 11:19 AM, Stephen Boyd wrote:
Quoting Akhil P Oommen (2022-07-18 21:07:05)
On 7/14/2022 11:10 AM, Akhil P Oommen wrote:
On 7/12/2022 4:57 AM, Doug Anderson wrote:
Hi,
On Fri, Jul 8, 2022 at 11:00 PM Akhil P Oommen
wrote:
Update gpu register array with gpucc memory region
On 7/19/2022 3:26 PM, Rajendra Nayak wrote:
On 7/19/2022 12:49 PM, Stephen Boyd wrote:
Quoting Akhil P Oommen (2022-07-18 23:37:16)
On 7/19/2022 11:19 AM, Stephen Boyd wrote:
Quoting Akhil P Oommen (2022-07-18 21:07:05)
On 7/14/2022 11:10 AM, Akhil P Oommen wrote:
IIUC, qcom gdsc driver
On 7/20/2022 11:36 PM, Rob Clark wrote:
On Tue, Jul 12, 2022 at 12:15 PM Akhil P Oommen
wrote:
On 7/12/2022 10:14 PM, Rob Clark wrote:
On Mon, Jul 11, 2022 at 10:05 PM Akhil P Oommen
wrote:
On 7/12/2022 4:52 AM, Doug Anderson wrote:
Hi,
On Fri, Jul 8, 2022 at 11:00 PM Akhil P Oommen
On 7/20/2022 11:34 AM, Akhil P Oommen wrote:
On 7/19/2022 3:26 PM, Rajendra Nayak wrote:
On 7/19/2022 12:49 PM, Stephen Boyd wrote:
Quoting Akhil P Oommen (2022-07-18 23:37:16)
On 7/19/2022 11:19 AM, Stephen Boyd wrote:
Quoting Akhil P Oommen (2022-07-18 21:07:05)
On 7/14/2022 11:10 AM
On 7/21/2022 2:08 AM, Akhil P Oommen wrote:
On 7/20/2022 11:36 PM, Rob Clark wrote:
On Tue, Jul 12, 2022 at 12:15 PM Akhil P Oommen
wrote:
On 7/12/2022 10:14 PM, Rob Clark wrote:
On Mon, Jul 11, 2022 at 10:05 PM Akhil P Oommen
wrote:
On 7/12/2022 4:52 AM, Doug Anderson wrote:
Hi,
On Fri
driver can expose an interface to the client driver using
reset framework. Using this the client driver can trigger a polling within
the gdsc driver.
This series is rebased on top of linus's master branch.
Related discussion: https://patchwork.freedesktop.org/patch/493144/
Akhil P Oomm
Add necessary definitions in gpucc bindings to ensure gpu cx gdsc collapse
through 'reset' framework for SC7280.
Signed-off-by: Akhil P Oommen
---
include/dt-bindings/clock/qcom,gpucc-sc7280.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings/clock/qcom,gpuc
Add support to allow soc specific clk drivers to specify a custom reset
operation. A consumer-driver of the reset framework can call
"reset_control_reset()" api to trigger this.
Signed-off-by: Akhil P Oommen
---
drivers/clk/qcom/reset.c | 6 ++
drivers/clk/qcom/reset.h | 2 +
Add a reset op compatible function to poll for gdsc collapse.
Signed-off-by: Akhil P Oommen
---
drivers/clk/qcom/gdsc.c | 23 +++
drivers/clk/qcom/gdsc.h | 7 +++
2 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom
Add support for Reset using GPUCC driver for GPU. This helps to ensure
that GPU state is reset by making sure that CX head switch is collapsed.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom
Allow a consumer driver to poll for cx gdsc collapse through Reset
framework.
Signed-off-by: Akhil P Oommen
---
drivers/clk/qcom/gpucc-sc7280.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c
index 9a832f2..f5df51d
count for all active submits
Changes in v2:
- Rebased on msm-next tip
Akhil P Oommen (8):
drm/msm: Remove unnecessary pm_runtime_get/put
drm/msm: Take single rpm refcount on behalf of all submits
drm/msm: Correct pm_runtime votes in recover worker
drm/msm: Fix cx collapse issue during recovery
Instead of separate refcount for each submit, take single rpm refcount
on behalf of all the submits. This makes it easier to drop the rpm
refcount during recovery in an upcoming patch.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/msm_gpu.c | 12
1
igned-off-by: Akhil P Oommen
---
Changes in v3:
- Use reset interface from gpucc driver to poll for cx gdsc collapse
https://patchwork.freedesktop.org/series/106860/
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4
drivers/gpu/drm/msm/msm_gpu.c | 4
drivers/gpu/drm/msm/msm_
In the scenario where there is one a single submit which is hung, gpu is
power collapsed when it is retired. Because of this, by the time we call
reover(), gpu state would be already clear. Fix this by correctly
managing the pm runtime votes.
Signed-off-by: Akhil P Oommen
---
(no changes since
We already enable gpu power from msm_gpu_submit(), so avoid a duplicate
pm_runtime_get/put from msm_job_run().
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/msm_ringbuffer.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/msm
We can do a few more things to improve our chance at a successful gpu
recovery, especially during a hangcheck timeout:
1. Halt CP and GMU core
2. Do RBBM GBIF HALT sequence
3. Do a soft reset of GPU core
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno
n gpu and its
smmu. So the *struct gpu device* needs to be runtime suspended to ensure
that the iommu driver removes its vote on cx gdsc.
Signed-off-by: Akhil P Oommen
---
Changes in v3:
- Simplied the pm refcount drop since we have just a single refcount now
for all active submits
drivers/gpu/dr
When prepare-slumber hfi fails, we should follow a6xx_gmu_force_off()
sequence.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b
WARN(gpu->active_submits) during runtime_suspend doesn't make sense now
because we force runtime suspend during a gpu recovery when there are
active submissions pending.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/adreno_device.c | 7 ---
On 7/31/2022 9:25 PM, Rob Clark wrote:
On Sat, Jul 30, 2022 at 2:41 AM Akhil P Oommen wrote:
We already enable gpu power from msm_gpu_submit(), so avoid a duplicate
pm_runtime_get/put from msm_job_run().
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm
On 8/1/2022 3:45 AM, Rob Clark wrote:
On Sun, Jul 31, 2022 at 9:33 AM Akhil P Oommen wrote:
On 7/31/2022 9:26 PM, Rob Clark wrote:
On Sat, Jul 30, 2022 at 2:41 AM Akhil P Oommen wrote:
Instead of separate refcount for each submit, take single rpm refcount
on behalf of all the submits. This
On 7/31/2022 9:52 PM, Rob Clark wrote:
On Sat, Jul 30, 2022 at 2:41 AM Akhil P Oommen wrote:
There are some hardware logic under CX domain. For a successful
recovery, we should ensure cx headswitch collapses to ensure all the
stale states are cleard out. This is especially true to for a6xx
applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Akhil-P-Oommen/clk-qcom-Support-gdsc-collap
On 8/3/2022 12:02 AM, Rob Clark wrote:
On Tue, Aug 2, 2022 at 12:02 AM Dmitry Baryshkov
wrote:
On 30/07/2022 12:17, Akhil P Oommen wrote:
Some clients like adreno gpu driver would like to ensure that its gdsc
is collapsed at hardware during a gpu reset sequence. This is because it
has a
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