Re: [PATCH v2 2/3] drm/msm/dsi: Set PHY usescase (and mode) before registering DSI host

On Sun, Feb 09, 2025 at 10:42:53PM +0100, Marijn Suijten wrote: > Ordering issues here cause an uninitialized (default STANDALONE) > usecase to be programmed (which appears to be a MUX) in some cases > when msm_dsi_host_register() is called, leading to the slave PLL in > bonded-DSI mode to source f

Re: [PATCH v2 3/3] drm/msm/dpu: Remove arbitrary limit of 1 interface in DSC topology

On Sun, Feb 09, 2025 at 10:42:54PM +0100, Marijn Suijten wrote: > When DSC is enabled the number of interfaces is forced to be 1, and > documented that it is a "power-optimal" layout to use two DSC encoders > together with two Layer Mixers. However, the same layout (two DSC > hard-slice encoders w

[PATCH v2 1/3] drm/msm/dsi: Use existing per-interface slice count in DSC timing

When configuring the timing of DSI hosts (interfaces) in dsi_timing_setup() all values written to registers are taking bonded-mode into account by dividing the original mode width by 2 (half the data is sent over each of the two DSI hosts), but the full width instead of the interface width is passe

[PATCH v2 2/3] drm/msm/dsi: Set PHY usescase (and mode) before registering DSI host

Ordering issues here cause an uninitialized (default STANDALONE) usecase to be programmed (which appears to be a MUX) in some cases when msm_dsi_host_register() is called, leading to the slave PLL in bonded-DSI mode to source from a clock parent (dsi1vco) that is off. This should seemingly not be

[PATCH v2 3/3] drm/msm/dpu: Remove arbitrary limit of 1 interface in DSC topology

When DSC is enabled the number of interfaces is forced to be 1, and documented that it is a "power-optimal" layout to use two DSC encoders together with two Layer Mixers. However, the same layout (two DSC hard-slice encoders with two LMs) is also used when the display is fed with data over two ins

[PATCH v2 0/3] drm/msm: Initial fixes for DUALPIPE (+DSC) topology

This series covers a step-up towards supporting the DUALPIPE DSC topology, also known as 2:2:2 topology (on active-CTL hardware). It involves 2 layer mixers, 2 DSC compression encoders, and 2 interfaces (on DSI, this is called bonded-DSI) where bandwidth constraints (e.g. 4k panels at 120Hz) requi

Re: [PATCH] drm/msm/dpu: Fix uninitialized variable

thin the loop and return explicit 0 if there was no error. > > for (i = 0; i < num_planes; i++) { > struct drm_plane_state *plane_state = states[i]; > > --- > base-commit: a64dcfb451e254085a7daee5fe51bf22959d52d3 > change-id: 20250209-dpu-c3fac78fc617 > > Best regards, > -- > Ethan Carter Edwards > -- With best wishes Dmitry

Re: [PATCH v2] drm/msm/dpu: Fix uninitialized variable

alar variable") > Fixes: 774bcfb731765d ("drm/msm/dpu: add support for virtual planes") > Signed-off-by: Ethan Carter Edwards > --- > Changes in v2: > - Return explicit 0 when no error occurs > - Add hardening mailing lists > - Link to v1: > https://lore

Re: [PATCH v2 2/3] drm/msm/dsi: Set PHY usescase (and mode) before registering DSI host

On 2/9/2025 1:42 PM, Marijn Suijten wrote: Ordering issues here cause an uninitialized (default STANDALONE) usecase to be programmed (which appears to be a MUX) in some cases when msm_dsi_host_register() is called, leading to the slave PLL in bonded-DSI mode to source from a clock parent (dsi1

[PATCH v2 1/3] drm/display: bridge-connector: add DisplayPort bridges

DRM HDMI Codec framework is useful not only for the HDMI bridges, but also for the DisplayPort bridges. Add new DRM_BRIDGE_OP_DisplayPort define in order to distinguish DP bridges. Create HDMI codec device automatically for DP bridges which have declared audio support. Note, unlike HDMI devices, w

[PATCH v2 3/3] drm/msm/dp: reuse generic HDMI codec implementation

The MSM DisplayPort driver implements several HDMI codec functions in the driver, e.g. it manually manages HDMI codec device registration, returning ELD and plugged_cb support. In order to reduce code duplication reuse drm_hdmi_audio_* helpers and drm_bridge_connector integration. As a part of thi

[PATCH v2 0/3] drm/bridge: reuse DRM HDMI Audio helpers for DisplayPort bridges

A lot of DisplayPort bridges use HDMI Codec in order to provide audio support. Present DRM HDMI Audio support has been written with the HDMI and in particular DRM HDMI Connector framework support, however those audio helpers can be easily reused for DisplayPort drivers too. Patches by Hermes Wu th

[PATCH v2 2/3] drm/display: bridge_connector: add DisplayPort subconnector property

Create the DisplayPort subconnector property for DP connectors managed through drm_bridge_connector, removing the need to create it manually by the drivers. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/display/drm_bridge_connector.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/dr

Re: [PATCH v2] drm/msm/dp: account for widebus and yuv420 during mode validation

On 06/02/2025 19:46, Abhinav Kumar wrote: Widebus allows the DP controller to operate in 2 pixel per clock mode. The mode validation logic validates the mode->clock against the max DP pixel clock. However the max DP pixel clock limit assumes widebus is already enabled. Adjust the mode validation

Re: [PATCH v3] drm/bridge-connector: handle subconnector types

On Fri, Jan 17, 2025 at 11:50:50AM +0200, Dmitry Baryshkov wrote: > If the created connector type supports subconnector type property, > create and attach corresponding it. The default subtype value is 0, > which maps to the DRM_MODE_SUBCONNECTOR_Unknown type. Also remove > subconnector creation fr

Re: [PATCH v3 2/2] arm64: dts: qcom: sa8775p-ride: Enable Adreno 663 GPU

On Wed, Nov 13, 2024 at 02:18:43AM +0530, Akhil P Oommen wrote: > On 10/30/2024 12:32 PM, Akhil P Oommen wrote: > > From: Puranam V G Tejaswi > > > > Enable GPU for sa8775p-ride platform and provide path for zap > > shader. > > > > Signed-off-by: Puranam V G Tejaswi > > Signed-off-by: Akhil P O