On 08/01/2025 21:39, Akhil P Oommen wrote:
ACD a.k.a Adaptive Clock Distribution is a feature which helps to reduce
the power consumption. In some chipsets, it is also a requirement to
support higher GPU frequencies. This patch adds support for GPU ACD by
sending necessary data to GMU and AOSS. T
On Thu, Jan 09, 2025 at 02:10:01AM +0530, Akhil P Oommen wrote:
> Add a new schema which extends opp-v2 to support a new vendor specific
> property required for Adreno GPUs found in Qualcomm's SoCs. The new
> property called "qcom,opp-acd-level" carries a u32 value recommended
> for each opp needs
On 08/01/2025 21:39, Akhil P Oommen wrote:
When ACD feature is enabled, it triggers some internal calibrations
which result in a pretty long delay during the first HFI perf vote.
So, increase the HFI response timeout to match the downstream driver.
Signed-off-by: Akhil P Oommen
---
drivers/gp
On 1/9/2025 2:13 PM, Dmitry Baryshkov wrote:
On Thu, 9 Jan 2025 at 23:26, Jessica Zhang wrote:
On 12/28/2024 8:47 PM, Dmitry Baryshkov wrote:
On Thu, Dec 26, 2024 at 02:49:28PM -0800, Jessica Zhang wrote:
On 12/20/2024 5:07 PM, Dmitry Baryshkov wrote:
On Fri, Dec 20, 2024 at 04:12:29
On 1/9/2025 5:42 PM, Dmitry Baryshkov wrote:
On Fri, 10 Jan 2025 at 02:30, Jessica Zhang wrote:
On 1/9/2025 4:00 PM, Dmitry Baryshkov wrote:
On Thu, Jan 09, 2025 at 02:34:44PM -0800, Jessica Zhang wrote:
On 1/3/2025 10:16 AM, Dmitry Baryshkov wrote:
On Fri, Jan 03, 2025 at 10:03:35AM
On Fri, 10 Jan 2025 at 02:30, Jessica Zhang wrote:
>
>
>
> On 1/9/2025 4:00 PM, Dmitry Baryshkov wrote:
> > On Thu, Jan 09, 2025 at 02:34:44PM -0800, Jessica Zhang wrote:
> >>
> >>
> >> On 1/3/2025 10:16 AM, Dmitry Baryshkov wrote:
> >>> On Fri, Jan 03, 2025 at 10:03:35AM -0800, Jessica Zhang wrot
On Thu, Jan 09, 2025 at 05:40:23PM -0800, Abhinav Kumar wrote:
>
>
> On 1/5/2025 7:07 PM, Dmitry Baryshkov wrote:
> > The fix_core_ab_vote is an average bandwidth value, used for bandwidth
> > overrides in several cases. However there is an internal inconsistency:
> > fix_core_ib_vote is defined
On Thu, Jan 09, 2025 at 02:53:16PM +0100, Thomas Zimmermann wrote:
> Hi
>
>
> Am 22.12.24 um 06:00 schrieb Dmitry Baryshkov:
> > As pointed out by Simona, the drm_atomic_helper_check_modeset() and
> > drm_atomic_helper_check() require the former function is rerun if the
> > driver's callbacks mod
On Thu, Jan 09, 2025 at 02:34:44PM -0800, Jessica Zhang wrote:
>
>
> On 1/3/2025 10:16 AM, Dmitry Baryshkov wrote:
> > On Fri, Jan 03, 2025 at 10:03:35AM -0800, Jessica Zhang wrote:
> > >
> > >
> > > On 12/19/2024 9:03 PM, Dmitry Baryshkov wrote:
> > > > On Mon, Dec 16, 2024 at 04:43:26PM -0800
On Thu, Jan 09, 2025 at 02:53:40PM -0800, Jessica Zhang wrote:
>
>
> On 1/9/2025 2:13 PM, Dmitry Baryshkov wrote:
> > On Thu, 9 Jan 2025 at 23:26, Jessica Zhang
> > wrote:
> > >
> > >
> > >
> > > On 12/28/2024 8:47 PM, Dmitry Baryshkov wrote:
> > > > On Thu, Dec 26, 2024 at 02:49:28PM -0800,
On 1/5/2025 7:07 PM, Dmitry Baryshkov wrote:
The IB values in core_perf calculations (max_per_pipe_ib,
fix_core_ib_vote) are expressed in KBps and are passed to icc_set_bw
without additional division. Change type of those values to u32.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/m
On 1/5/2025 7:07 PM, Dmitry Baryshkov wrote:
The fix_core_ab_vote is an average bandwidth value, used for bandwidth
overrides in several cases. However there is an internal inconsistency:
fix_core_ib_vote is defined in KBps, while fix_core_ab_vote is defined
in Bps.
Fix that by changing the t
On 1/5/2025 7:07 PM, Dmitry Baryshkov wrote:
The code in dpu_core_perf_crtc_check() mostly duplicates code in
dpu_core_perf_aggregate(). Remove the duplication by reusing the latter
function.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 94 +++
From: Rob Clark
If userspace is trying to achieve a timeout of zero, let 'em have it.
Only round up if the timeout is greater than zero.
Fixes: 4969bccd5f4e ("drm/msm: Avoid rounding down to zero jiffies")
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.h | 10 --
1 file chang
On 12/28/2024 8:47 PM, Dmitry Baryshkov wrote:
On Thu, Dec 26, 2024 at 02:49:28PM -0800, Jessica Zhang wrote:
On 12/20/2024 5:07 PM, Dmitry Baryshkov wrote:
On Fri, Dec 20, 2024 at 04:12:29PM -0800, Jessica Zhang wrote:
On 12/19/2024 9:52 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 202
On Thu, Jan 09, 2025 at 02:08:36PM +0100, Krzysztof Kozlowski wrote:
> Add DPU version v12.0 support for the Qualcomm SM8750 platform.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> .../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h| 522
> +
> drivers/gpu/drm/msm/disp/dpu1
On 1/3/2025 10:16 AM, Dmitry Baryshkov wrote:
On Fri, Jan 03, 2025 at 10:03:35AM -0800, Jessica Zhang wrote:
On 12/19/2024 9:03 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 at 04:43:26PM -0800, Jessica Zhang wrote:
Add the cwb_enabled flag to msm_display topology and adjust the toplog
On Thu, Jan 09, 2025 at 02:08:37PM +0100, Krzysztof Kozlowski wrote:
> Add support for the Qualcomm SM8750 platform.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 33 +
> drivers/gpu/drm/msm/msm_mdss.h | 1 +
> 2 files changed, 3
On 1/9/2025 4:00 PM, Dmitry Baryshkov wrote:
On Thu, Jan 09, 2025 at 02:34:44PM -0800, Jessica Zhang wrote:
On 1/3/2025 10:16 AM, Dmitry Baryshkov wrote:
On Fri, Jan 03, 2025 at 10:03:35AM -0800, Jessica Zhang wrote:
On 12/19/2024 9:03 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 a
On Thu, 9 Jan 2025 at 23:26, Jessica Zhang wrote:
>
>
>
> On 12/28/2024 8:47 PM, Dmitry Baryshkov wrote:
> > On Thu, Dec 26, 2024 at 02:49:28PM -0800, Jessica Zhang wrote:
> >>
> >>
> >> On 12/20/2024 5:07 PM, Dmitry Baryshkov wrote:
> >>> On Fri, Dec 20, 2024 at 04:12:29PM -0800, Jessica Zhang wr
Am Donnerstag, 9. Januar 2025, 15:57:13 CET schrieb Thomas Zimmermann:
> Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
> buffer size. Align the pitch to a multiple of 64.
>
> Signed-off-by: Thomas Zimmermann
> Cc: Sandy Huang
> Cc: "Heiko Stübner"
> Cc: Andy Yan
I've loo
On Thu, Jan 09, 2025 at 02:08:38PM +0100, Krzysztof Kozlowski wrote:
> Not finished. Looking around, maybe someone already did some works
> around new CTL_PIPE_ACTIVE and CTL_LAYER_ACTIVE registers?
This is not enough, the whole blend setup is to be moved to LM
block.
>
> Signed-off-by: Krzyszto
On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
> differences worth noting:
>
> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
>offsets were just switched. Currently these r
On Thu, Jan 09, 2025 at 05:50:16PM -0800, Jessica Zhang wrote:
>
>
> On 1/9/2025 5:42 PM, Dmitry Baryshkov wrote:
> > On Fri, 10 Jan 2025 at 02:30, Jessica Zhang
> > wrote:
> > >
> > >
> > >
> > > On 1/9/2025 4:00 PM, Dmitry Baryshkov wrote:
> > > > On Thu, Jan 09, 2025 at 02:34:44PM -0800,
/msm/msm_mdss.h | 1 +
.../gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 14 +
21 files changed, 1335 insertions(+), 79 deletions(-)
---
base-commit: c38a35d266317199e72729fbbca5b2337c20a6d9
change-id: 20250109-b4-sm8750-display-6ea537754af1
Best regards,
--
Krzysztof
Add support for the Qualcomm SM8750 platform.
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/msm_mdss.c | 33 +
drivers/gpu/drm/msm/msm_mdss.h | 1 +
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/
Not finished. Looking around, maybe someone already did some works
around new CTL_PIPE_ACTIVE and CTL_LAYER_ACTIVE registers?
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h | 12 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
Several devices have the same clock inputs, thus they can be in the same
if:then: clause, making everything smaller. No functional impact.
Signed-off-by: Krzysztof Kozlowski
---
.../bindings/display/msm/dsi-controller-main.yaml | 64 ++
1 file changed, 5 insertions(+), 59 d
Add DPU for Qualcomm SM8750 SoC which has several differences, new
blocks and changes in registers, making it incompatible with SM8650.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Do
Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
differences worth noting:
1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
offsets were just switched. Currently these registers are not used
in the driver, so the easiest is to document both but
Add DPU version v12.0 support for the Qualcomm SM8750 platform.
Signed-off-by: Krzysztof Kozlowski
---
.../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h| 522 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 35 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |
Specific constrain in if:then: blocks for variable lists, like clocks
and clock-names, should have a fixed upper and lower size. Older
dtschema implied minItems, but that's not true since 2024 and missing
minItems means that lower bound is not set.
Signed-off-by: Krzysztof Kozlowski
---
.../dev
Add DSI controller for Qualcomm SM8750 SoC which is quite different from
previous (SM8650) generation.
It does not allow the display clock controller clocks like "byte" and
"pixel" to be reparented to DSI PHY PLLs while the DSI PHY PLL is not
configured (not prepared, rate not set). Therefore
ass
Add DSI PHY v7.0 for Qualcomm SM8750 SoC which is quite different from
previous (SM8650) generation.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display
Hi Akhil,
kernel test robot noticed the following build warnings:
[auto build test WARNING on dbfac60febfa806abb2d384cb6441e77335d2799]
url:
https://github.com/intel-lab-lkp/linux/commits/Akhil-P-Oommen/drm-msm-adreno-Add-support-for-ACD/20250109-044339
base
On 1/9/2025 1:36 PM, Krzysztof Kozlowski wrote:
> On Thu, Jan 09, 2025 at 02:10:01AM +0530, Akhil P Oommen wrote:
>> Add a new schema which extends opp-v2 to support a new vendor specific
>> property required for Adreno GPUs found in Qualcomm's SoCs. The new
>> property called "qcom,opp-acd-level"
On 8.01.2025 9:40 PM, Akhil P Oommen wrote:
> Add a module param to disable ACD which will help to quickly rule it
> out for any GPU issues.
>
> Signed-off-by: Akhil P Oommen
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++
> drivers/gpu/drm/msm/adreno/adreno_device.c | 4
>
Add DisplayPort controller for Qualcomm SM8750 SoC which so far looks
fully compatible with earlier SM8650 variant.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/device
On 8.01.2025 9:40 PM, Akhil P Oommen wrote:
> Update GPU node to include acd level values.
>
> Signed-off-by: Akhil P Oommen
> ---
Reviewed-by: Konrad Dybcio
Konrad
Add MDSS/MDP display subsystem for Qualcomm SM8750 SoC, next generation
with two revisions up of the IP block comparing to SM8650.
Signed-off-by: Krzysztof Kozlowski
---
.../bindings/display/msm/qcom,sm8750-mdss.yaml | 460 +
1 file changed, 460 insertions(+)
diff --git
On 12/18/2024 11:49 PM, Jun Nie wrote:
There are 2 interfaces and 4 pingpong in quad pipe. Map the 2nd
interface to 3rd PP instead of the 2nd PP.
Signed-off-by: Jun Nie
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 15 +
Hi
Am 22.12.24 um 06:00 schrieb Dmitry Baryshkov:
As pointed out by Simona, the drm_atomic_helper_check_modeset() and
drm_atomic_helper_check() require the former function is rerun if the
driver's callbacks modify crtc_state->mode_changed. MSM is one of the
drivers which failed to follow this r
On 8.01.2025 11:42 PM, Akhil P Oommen wrote:
> Adreno X1-85 has an additional bit which is at a non-contiguous
> location in qfprom. Add support for this new "hi" bit along with
> the speedbin mappings.
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +
> drivers/gpu/drm/msm/adreno/adre
On 09/01/2025 23:39, Dmitry Baryshkov wrote:
> On Thu, Jan 09, 2025 at 02:08:37PM +0100, Krzysztof Kozlowski wrote:
>> Add support for the Qualcomm SM8750 platform.
>>
>> Signed-off-by: Krzysztof Kozlowski
>> ---
>> drivers/gpu/drm/msm/msm_mdss.c | 33 +
>> drivers
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 128.
The hibmc driver's new hibmc_dumb_create() is similar to the one
in GEM VRAM helpers. The driver was the only caller of
drm_gem_vram_fill_create_dumb(). Remove the now unused help
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. The hardware requires the scnaline pitch to be a multiple
of 32 pixels. Therefore compute the byte size of 32 pixels in the given
color mode and align the pitch accordingly.
Signed-off-by: Thomas Zimmermann
Cc: Rob C
The ioctls MODE_CREATE_DUMB and MODE_MAP_DUMB return results into a
memory buffer supplied by user space. On errors, it is possible that
intermediate values are being returned. The exact semantics depends
on the DRM driver's implementation of these ioctls. Although this is
most-likely not a securit
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 64.
Signed-off-by: Thomas Zimmermann
Cc: Sandy Huang
Cc: "Heiko Stübner"
Cc: Andy Yan
---
drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 12 ++--
1 file changed, 6 insertio
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 8.
Push the current calculation into the only direct caller imx. Imx's
hardware requires the framebuffer width to be aligned to 8. The
driver's current approach is actually incorrect,
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.
Signed-off-by: Thomas Zimmermann
Cc: Laurent Pinchart
Cc: Kieran Bingham
---
drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c | 7 +--
1 file changed, 5 inserti
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. No alignment required.
Signed-off-by: Thomas Zimmermann
Cc: Russell King
---
drivers/gpu/drm/armada/armada_gem.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.
Signed-off-by: Thomas Zimmermann
Cc: Laurent Pinchart
Cc: Tomi Valkeinen
---
drivers/gpu/drm/xlnx/zynqmp_kms.c | 7 +--
1 file changed, 5 insertions(+), 2 de
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. Align the pitch to a multiple of 8. Align the
buffer size according to hardware requirements.
Signed-off-by: Thomas Zimmermann
Cc: Lucas De Marchi
Cc: "Thomas Hellström"
Cc: Rodrigo Vivi
---
drivers/gpu/drm/xe/xe
Dumb-buffer pitch and size is specified by width, height, bits-per-pixel
plus various hardware-specific alignments. The calculation of these
values is inconsistent and duplicated among drivers. The results for
formats with bpp < 8 are incorrect.
This series fixes this for most drivers. Default sca
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 8.
Signed-off-by: Thomas Zimmermann
Cc: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_gem.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/dri
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. Align the pitch to a multiple of 8.
Signed-off-by: Thomas Zimmermann
Cc: Oleksandr Andrushchenko
---
drivers/gpu/drm/xen/xen_drm_front.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/dr
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.
Signed-off-by: Thomas Zimmermann
Cc: Sui Jingfeng
Cc: Sui Jingfeng
---
drivers/gpu/drm/loongson/lsdc_gem.c | 29 -
1 file changed, 8
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. No alignment required.
Signed-off-by: Thomas Zimmermann
Cc: Dave Airlie
Cc: Gerd Hoffmann
---
drivers/gpu/drm/qxl/qxl_dumb.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/dr
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 4.
Signed-off-by: Thomas Zimmermann
Cc: David Airlie
Cc: Gerd Hoffmann
Cc: Gurchetan Singh
Cc: Chia-I Wu
---
drivers/gpu/drm/virtio/virtgpu_gem.c | 11 +--
1 file changed
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. No alignment required.
Signed-off-by: Thomas Zimmermann
Cc: Zack Rusin
Cc: Broadcom internal kernel review list
---
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 21 -
1 file changed, 4 insertions(
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.
Signed-off-by: Thomas Zimmermann
Cc: Thierry Reding
Cc: Mikko Perttunen
---
drivers/gpu/drm/tegra/gem.c | 8 +---
1 file changed, 5 insertions(+), 3 deletion
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 256.
Signed-off-by: Thomas Zimmermann
Cc: Karol Herbst
Cc: Lyude Paul
Cc: Danilo Krummrich
---
drivers/gpu/drm/nouveau/nouveau_display.c | 7 ---
1 file changed, 4 insertions(
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.
Signed-off-by: Thomas Zimmermann
Cc: Biju Das
---
drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 8.
Signed-off-by: Thomas Zimmermann
Cc: Chun-Kuang Hu
Cc: Philipp Zabel
Cc: Matthias Brugger
Cc: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_gem.c | 13 --
Add drm_modes_size_dumb(), a helper to calculate the dumb-buffer
scanline pitch and allocation size. Implementations of struct
drm_driver.dumb_create can call the new helper for their size
computations. There's currently quite a bit of code duplication
among DRM's memory managers. Each calculates s
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Inline code from drm_gem_vram_fill_create_dumb() without
the existing size computation. Align the pitch to a multiple of 8.
Only hibmc and vboxvideo use gem-vram. Hibmc invokes the call to
drm_gem_vram_fill_create_dum
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 8.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_gem_shmem_helper.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/d
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 64.
Signed-off-by: Thomas Zimmermann
Cc: Patrik Jakobsson
---
drivers/gpu/drm/gma500/gem.c | 21 ++---
1 file changed, 6 insertions(+), 15 deletions(-)
diff --git a
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. The hardware requires the framebuffer width to be a
multiple of 8. The scanline pitch has be large enough to support
this. Therefore compute the byte size of 8 pixels in the given color
mode and align the pitch accordi
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. No alignment required.
Signed-off-by: Thomas Zimmermann
Cc: Inki Dae
Cc: Seung-Woo Kim
Cc: Kyungmin Park
Cc: Krzysztof Kozlowski
Cc: Alim Akhtar
---
drivers/gpu/drm/exynos/exynos_drm_gem.c | 8 +---
1 file
On Wed, Jan 08, 2025 at 09:22:56PM -0800, Abhinav Kumar wrote:
>
>
> On 1/8/2025 8:26 PM, Dmitry Baryshkov wrote:
> > On Wed, Jan 08, 2025 at 08:11:27PM -0800, Abhinav Kumar wrote:
> > >
> > >
> > > On 1/8/2025 6:27 PM, Abhinav Kumar wrote:
> > > >
> > > >
> > > > On 12/21/2024 9:00 PM, Dmitr
On 25-01-08 16:17:47, Bjorn Andersson wrote:
> On Wed, Jan 08, 2025 at 04:31:43PM +0200, Abel Vesa wrote:
> > According to the DisplayPort standard, LTTPRs have two operating
> > modes:
> > - non-transparent - it replies to DPCD LTTPR field specific AUX
> >requests, while passes through all ot
On Thu, Jan 09, 2025 at 12:35:48PM +0800, Jun Nie wrote:
> Jessica Zhang 于2025年1月9日周四 07:41写道：
> >
> >
> >
> > On 12/19/2024 2:09 PM, Dmitry Baryshkov wrote:
> > > On Thu, Dec 19, 2024 at 03:49:22PM +0800, Jun Nie wrote:
> > >> decide right side of a pair per last bit, in case of multiple
> > >> m
On 25-01-08 14:57:41, Abhinav Kumar wrote:
>
>
> On 1/8/2025 6:31 AM, Abel Vesa wrote:
> > Link Training Tunable PHY Repeaters (LTTPRs) are defined in DisplayPort
> > 1.4a specification. As the name suggests, these PHY repeaters are
> > capable of adjusting their output for link training purposes
On Thu, Jan 09, 2025 at 12:40:23PM +0800, Jun Nie wrote:
> Jessica Zhang 于2025年1月9日周四 09:29写道：
> >
> >
> >
> > On 12/18/2024 11:49 PM, Jun Nie wrote:
> > > Add the case to reserve multiple pairs mixers for high resolution.
> > > Current code only supports one pair of mixer usage case. To support
>
On Wed, Jan 8, 2025 at 7:14 PM Abhinav Kumar wrote:
>
>
>
> On 1/8/2025 7:04 PM, Rob Clark wrote:
> > On Wed, Jan 8, 2025 at 6:22 PM Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 1/8/2025 6:14 PM, Dmitry Baryshkov wrote:
> >>> On Thu, 9 Jan 2025 at 03:45, Rob Clark wrote:
>
> On Wed
On 09/01/2025 14:13, Akhil P Oommen wrote:
> On 1/9/2025 1:36 PM, Krzysztof Kozlowski wrote:
>> On Thu, Jan 09, 2025 at 02:10:01AM +0530, Akhil P Oommen wrote:
>>> Add a new schema which extends opp-v2 to support a new vendor specific
>>> property required for Adreno GPUs found in Qualcomm's SoCs.
Hi
Am 09.01.25 um 17:05 schrieb Matthew Auld:
On 09/01/2025 14:57, Thomas Zimmermann wrote:
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. Align the pitch to a multiple of 8. Align the
buffer size according to hardware requirements.
Signed-off-by: Thomas Zimm
On 1/9/2025 1:24 PM, neil.armstr...@linaro.org wrote:
> On 08/01/2025 21:39, Akhil P Oommen wrote:
>> When ACD feature is enabled, it triggers some internal calibrations
>> which result in a pretty long delay during the first HFI perf vote.
>> So, increase the HFI response timeout to match the down
On 25-01-08 16:25:31, Bjorn Andersson wrote:
> On Wed, Jan 08, 2025 at 04:31:46PM +0200, Abel Vesa wrote:
> > Link Training Tunable PHY Repeaters (LTTPRs) are defined in DisplayPort
> > 1.4a specification. As the name suggests, these PHY repeaters are
> > capable of adjusting their output for link
80 matches
Mail list logo
