[PATCH 0/4] drm/msm/dpu: enable CDM for all supported platforms

Enable CDM block on all the platforms where it is supposed to be present. Notably, from the platforms being supported by the DPU driver it is not enabled for SM6115 (DPU 6.3), QCM2290 (DPU 6.5) and SM6375 (DPU 6.9) Signed-off-by: Dmitry Baryshkov --- Dmitry Baryshkov (4): drm/msm/dpu: renam

[PATCH 2/4] drm/msm/dpu: enable CDM_0 for all DPUs which are known to have it

Enable the CDM_0 block on all DPU generations which have the CDM block documented in the vendor dtsi file. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 + drivers/gpu/drm/msm/disp/

[PATCH 1/4] drm/msm/dpu: rename CDM block definition

The CDM block is not limited to SC7280, but it is common to all platforms that are known up to this point. Rename it from sc7280_cdm to dpu_cdm_0. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7

[PATCH 3/4] drm/msm/dpu: enable CDM_0 for SC8280XP platform

Enable CDM on the SC8280XP platform, allowing RGB to YUV conversion for the output. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers

[PATCH 4/4] drm/msm/dpu: enable CDM_0 for X Elite platform

Enable CDM on the X Elite platform, allowing RGB to YUV conversion for the output. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/

Re: [PATCH v4 06/25] drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation

On Mon, Dec 16, 2024 at 04:43:17PM -0800, Jessica Zhang wrote: > From: Dmitry Baryshkov > > Up to now the driver has been using encoder to allocate hardware > resources. Switch it to use CRTC id in preparation for the next step. > > Reviewed-by: Abhinav Kumar > Signed-off-by: Dmitry Baryshkov

Re: [PATCH v4 07/25] drm/msm/dpu: move resource allocation to CRTC

On Mon, Dec 16, 2024 at 04:43:18PM -0800, Jessica Zhang wrote: > From: Dmitry Baryshkov > > All resource allocation is centered around the LMs. Then other blocks > (except DSCs) are allocated basing on the LMs that was selected, and LM > powers up the CRTC rather than the encoder. > > Moreover i

Re: [PATCH 2/4] drm/msm/dp: remove redundant ST_DISPLAY_OFF checks in msm_dp_bridge_atomic_enable()

On Wed, Dec 04, 2024 at 12:32:55PM +0200, Dmitry Baryshkov wrote: > On Tue, Dec 03, 2024 at 07:24:46PM -0800, Abhinav Kumar wrote: > > > > > > On 12/3/2024 5:53 AM, Dmitry Baryshkov wrote: > > > On Mon, Dec 02, 2024 at 04:39:01PM -0800, Abhinav Kumar wrote: > > > > The checks in msm_dp_display_pr

Re: [PATCH v2 2/3] dt-bindings: opp: Add v2-qcom-adreno vendor bindings

On Mon, Dec 23, 2024 at 12:31:27PM +0100, Konrad Dybcio wrote: > On 4.12.2024 7:18 PM, Akhil P Oommen wrote: > > On 11/16/2024 1:17 AM, Dmitry Baryshkov wrote: > >> On Fri, 15 Nov 2024 at 19:54, Akhil P Oommen > >> wrote: > >>> > >>> On 11/15/2024 3:54 AM, Dmitry Baryshkov wrote: > Hello Akh

Re: [PATCH v2 2/3] dt-bindings: opp: Add v2-qcom-adreno vendor bindings

On 4.12.2024 7:18 PM, Akhil P Oommen wrote: > On 11/16/2024 1:17 AM, Dmitry Baryshkov wrote: >> On Fri, 15 Nov 2024 at 19:54, Akhil P Oommen >> wrote: >>> >>> On 11/15/2024 3:54 AM, Dmitry Baryshkov wrote: Hello Akhil, On Thu, 14 Nov 2024 at 20:50, Akhil P Oommen wrote:

Re: [PATCH v6 2/7] drm/msm: adreno: add plumbing to generate bandwidth vote table for GMU

On 17.12.2024 3:51 PM, Neil Armstrong wrote: > The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along > the Frequency and Power Domain level, but by default we leave the > OPP core scale the interconnect ddr path. > > While scaling via the interconnect path was sufficient, newer G

Re: [PATCH v6 6/7] arm64: qcom: dts: sm8550: add interconnect and opp-peak-kBps for GPU

On 17.12.2024 3:51 PM, Neil Armstrong wrote: > Each GPU OPP requires a specific peak DDR bandwidth, let's add > those to each OPP and also the related interconnect path. > > Reviewed-by: Akhil P Oommen > Signed-off-by: Neil Armstrong > --- Reviewed-by: Konrad Dybcio Konrad

Re: [PATCH v6 7/7] arm64: qcom: dts: sm8650: add interconnect and opp-peak-kBps for GPU

On 17.12.2024 3:51 PM, Neil Armstrong wrote: > Each GPU OPP requires a specific peak DDR bandwidth, let's add > those to each OPP and also the related interconnect path. > > Signed-off-by: Neil Armstrong > --- Reviewed-by: Konrad Dybcio Konrad

Re: [PATCH v6 4/7] drm/msm: adreno: find bandwidth index of OPP and set it along freq index

On 17.12.2024 3:51 PM, Neil Armstrong wrote: > The Adreno GPU Management Unit (GMU) can also scale the DDR Bandwidth > along the Frequency and Power Domain level, until now we left the OPP > core scale the OPP bandwidth via the interconnect path. > > In order to enable bandwidth voting via the GPU

Re: [PATCH v6 3/7] drm/msm: adreno: dynamically generate GMU bw table

On 17.12.2024 3:51 PM, Neil Armstrong wrote: > The Adreno GPU Management Unit (GMU) can also scale the ddr > bandwidth along the frequency and power domain level, but for > now we statically fill the bw_table with values from the > downstream driver. > > Only the first entry is used, which is a di

Re: [PATCH v3] drm/msm/a6xx: Add support for Adreno 612

On 12/21/2024 2:28 AM, Dmitry Baryshkov wrote: > On Fri, Dec 20, 2024 at 08:56:31PM +0100, Konrad Dybcio wrote: >> On 13.12.2024 12:46 PM, Akhil P Oommen wrote: >>> From: Jie Zhang >>> >>> Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets. >>> A612 falls under ADRENO_6XX_GEN1 family a

Re: [PATCH v2 2/3] dt-bindings: opp: Add v2-qcom-adreno vendor bindings

On 12/23/2024 5:24 PM, Dmitry Baryshkov wrote: > On Mon, Dec 23, 2024 at 12:31:27PM +0100, Konrad Dybcio wrote: >> On 4.12.2024 7:18 PM, Akhil P Oommen wrote: >>> On 11/16/2024 1:17 AM, Dmitry Baryshkov wrote: On Fri, 15 Nov 2024 at 19:54, Akhil P Oommen wrote: > > On 11/15/2024