On 2024/12/17 18:54, Dmitry Baryshkov wrote:
On Tue, Dec 10, 2024 at 02:53:56PM +0800, Fange Zhang wrote:
From: Li Liu
Add definitions for the display hardware used on the Qualcomm SM6150
platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Li Liu
Signed-off-by: Fange Zhang
---
.../
On Mon, Dec 16, 2024 at 10:27:28AM +0200, Dmitry Baryshkov wrote:
> Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
Please say something about why you're doing this and what the expected
outcome of doing so is.
There is currently no way for a third party (e.g. stable or distro
mainta
Hello Dmitry Baryshkov,
Commit 774bcfb73176 ("drm/msm/dpu: add support for virtual planes")
from Dec 15, 2024 (linux-next), leads to the following Smatch static
checker warning:
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:1062 dpu_plane_virtual_atomic_check()
error: 'plane_state' dereferencing pos
The Adreno GPU Management Unit (GMU) can also vote for DDR Bandwidth
along the Frequency and Power Domain level, but by default we leave the
OPP core scale the interconnect ddr path.
While scaling the interconnect path was sufficient, newer GPUs
like the A750 requires specific vote parameters and
Even if the code uses ARRAY_SIZE() to fill those tables,
it's still a best practice to not use magic values for
tables in structs.
Suggested-by: Dmitry Baryshkov
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Akhil P Oommen
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h |
The Adreno GPU Management Unit (GMU) can also scale the DDR Bandwidth
along the Frequency and Power Domain level, until now we left the OPP
core scale the OPP bandwidth via the interconnect path.
In order to enable bandwidth voting via the GPU Management
Unit (GMU), when an opp is set by devfreq w
Each GPU OPP requires a specific peak DDR bandwidth, let's add
those to each OPP and also the related interconnect path.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dts
Now all the DDR bandwidth voting via the GPU Management Unit (GMU)
is in place, declare the Bus Control Modules (BCMs) and the
corresponding parameters in the GPU info struct.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Akhil P Oommen
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/adreno
The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along
the Frequency and Power Domain level, but by default we leave the
OPP core scale the interconnect ddr path.
While scaling via the interconnect path was sufficient, newer GPUs
like the A750 requires specific vote paremeters and
Each GPU OPP requires a specific peak DDR bandwidth, let's add
those to each OPP and also the related interconnect path.
Reviewed-by: Akhil P Oommen
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm
The Adreno GPU Management Unit (GMU) can also scale the ddr
bandwidth along the frequency and power domain level, but for
now we statically fill the bw_table with values from the
downstream driver.
Only the first entry is used, which is a disable vote, so we
currently rely on scaling via the linux
On Tue, Dec 17, 2024 at 09:41:44AM +0100, Johan Hovold wrote:
> On Mon, Dec 16, 2024 at 10:27:28AM +0200, Dmitry Baryshkov wrote:
> > Link DSPP_2 to the LM_2 and DSPP_3 to the LM_3 mixer blocks.
>
> Please say something about why you're doing this and what the expected
> outcome of doing so is.
>
On Tue, 17 Dec 2024 at 13:02, fange zhang wrote:
>
>
>
> On 2024/12/17 18:54, Dmitry Baryshkov wrote:
> > On Tue, Dec 10, 2024 at 02:53:56PM +0800, Fange Zhang wrote:
> >> From: Li Liu
> >>
> >> Add definitions for the display hardware used on the Qualcomm SM6150
> >> platform.
> >>
> >> Reviewed
On Mon, 16 Dec 2024 16:43:15 -0800, Jessica Zhang wrote:
> Add a test for drm_atomic_check_modeset() specifically to validate
> drm_atomic_check_valid_clones() helper
>
> Signed-off-by: Jessica Zhang
Reviewed-by: Maxime Ripard
Thanks!
Maxime
On Sun, Dec 15, 2024 at 06:19:08PM -0800, Abhinav Kumar wrote:
> Hi Maxime
>
> Gentle reminder on this one.
>
> We are looking for some advice on how to go about KUnit for this static
> function.
>
> Please help with our question below.
>
> Thanks
>
> Abhinav
>
> On 12/6/2024 4:48 PM, Jessica
On Tue, Dec 10, 2024 at 02:53:56PM +0800, Fange Zhang wrote:
> From: Li Liu
>
> Add definitions for the display hardware used on the Qualcomm SM6150
> platform.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Li Liu
> Signed-off-by: Fange Zhang
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dp
The SM6150 platform doesn't have 3DMux (MERGE_3D) block, so it can not
split the screen between two LMs. Drop lm_pair fields as they don't make
sense for this platform.
Suggested-by: Abhinav Kumar
Fixes: cb2f9144693b ("drm/msm/dpu: Add SM6150 support")
Signed-off-by: Dmitry Baryshkov
---
Changes
From: Abhinav Kumar
In preparation to register a iommu fault handler for display
related modules, register a fault handler for the backing
mmu object of msm_kms.
Currently, the fault handler only captures the display snapshot
but we can expand this later if more information needs to be
added to
From: Abhinav Kumar
There is no recovery mechanism in place yet to recover from mmu
faults for DPU. We can only prevent the faults by making sure there
is no misconfiguration.
Rate-limit the snapshot capture for mmu faults to once per
msm_atomic_commit_tail() as that should be sufficient to capt
On 2024/12/13 18:19, Dmitry Baryshkov wrote:
On Fri, 13 Dec 2024 at 11:21, fange zhang wrote:
On 2024/12/10 19:02, Dmitry Baryshkov wrote:
On Tue, Dec 10, 2024 at 02:54:00PM +0800, Fange Zhang wrote:
From: Li Liu
Add display MDSS and DSI configuration for QCS615 RIDE board.
QCS615 has
| 3 +++
drivers/gpu/drm/msm/msm_mmu.h| 1 +
5 files changed, 52 insertions(+), 4 deletions(-)
---
base-commit: 86313a9cd152330c634b25d826a281c6a002eb77
change-id: 20241217-abhinavk-smmu-fault-handler-ade75fef9809
Best regards,
--
Jessica Zhang
From: Abhinav Kumar
Switch msm_kms to use msm_iommu_disp_new() so that the newly
registered fault handler will kick-in during any mmu faults.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_kms.c | 2 +-
1 file changed, 1 in
From: Abhinav Kumar
Introduce a new API msm_iommu_disp_new() for display use-cases.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_iommu.c | 26 ++
drivers/gpu/drm/msm/msm_mmu.h | 1 +
2 files cha
From: Abhinav Kumar
In preparation of registering a separate fault handler for
display, lets rename the existing msm_fault_handler to
msm_gpu_fault_handler.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_iommu.c | 6 +++---
On 12/17/2024 8:21 PM, Neil Armstrong wrote:
> The Adreno GPU Management Unit (GMU) can also scale the ddr
> bandwidth along the frequency and power domain level, but for
> now we statically fill the bw_table with values from the
> downstream driver.
>
> Only the first entry is used, which is a di
On 12/17/2024 2:21 AM, Rob Clark wrote:
> On Mon, Dec 16, 2024 at 12:25 PM Akhil P Oommen
> wrote:
>>
>> On 12/16/2024 10:28 PM, Connor Abbott wrote:
>>> On Mon, Dec 16, 2024 at 11:55 AM Akhil P Oommen
>>> wrote:
On 12/13/2024 10:40 PM, Antonino Maniscalco wrote:
> On 12/13/24 5:50
On Mon, 16 Dec 2024 16:43:14 -0800, Jessica Zhang wrote:
> Check that all encoders attached to a given CRTC are valid
> possible_clones of each other.
>
> Signed-off-by: Jessica Zhang
Reviewed-by: Maxime Ripard
Thanks!
Maxime
On Mon, 16 Dec 2024 16:43:13 -0800, Jessica Zhang wrote:
> Add kunit test to validate drm_crtc_in_clone_mode() helper
>
> Signed-off-by: Jessica Zhang
Reviewed-by: Maxime Ripard
Thanks!
Maxime
On Mon, 16 Dec 2024 16:43:12 -0800, Jessica Zhang wrote:
> Add a common helper to check if the given CRTC state is in clone mode.
> This can be used by drivers to help detect if a CRTC is being shared by
> multiple encoders
>
> Signed-off-by: Jessica Zhang
>
> [ ... ]
Reviewed-by: Maxime Ripard
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