This series introduces support to enable the Mobile Display Subsystem (MDSS)
and Display Processing Unit (DPU) for the Qualcomm SA8775P target. It
includes the addition of the hardware catalog, compatible string,
relevant device tree changes, and their YAML bindings.
---
In this series PATCH 5: "
Document the MDSS hardware found on the Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
[v2]
- Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry]
- Update bindings by fixing dt_binding_check tool errors (update includes in
example),
adding proper spacing and in
Add mdss0 and mdp devicetree nodes for sa8775p target.
Signed-off-by: Mahadevan
---
This patch depends on the clock enablement change:
https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/
---
[v2]
- Update commit message mentioning enablement of mdss0 only is done
Add Mobile Display Subsystem (MDSS) support for the SA8775P platform.
Signed-off-by: Mahadevan
---
[v2]
- Update commit message. [Dmitry]
- Reorder compatible string of MDSS based on alphabetical order. [Dmitry]
- add reg_bus_bw in msm_mdss_data. [Dmitry]
---
drivers/gpu/drm/msm/msm_mdss.c | 1
Add definitions for the display hardware used on the
Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
[v2]
- Reorder compatible string of DPU based on alphabetical order.[Dmitry]
---
.../msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw
Document the DPU for Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
[v2]
- Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry]
- Update bindings by fixing dt_binding_check tool errors (update includes in
example),
adding proper spacing and indentation in bindin
This series introduces support to enable the Mobile Display Subsystem (MDSS)
and Display Processing Unit (DPU) for the Qualcomm SA8775P target. It
includes the addition of the hardware catalog, compatible string,
relevant device tree changes, and their YAML bindings.
---
In this series PATCH 5: "
On Wed, Sep 25, 2024 at 02:49:48PM GMT, Abhinav Kumar wrote:
> On 9/25/2024 2:11 PM, Dmitry Baryshkov wrote:
> > On Wed, 25 Sept 2024 at 22:39, Jessica Zhang
> > wrote:
> > > On 9/24/2024 4:13 PM, Dmitry Baryshkov wrote:
> > > > On Tue, Sep 24, 2024 at 03:59:21PM GMT, Jessica Zhang wrote:
> > > >
On Thu, Sep 26, 2024 at 04:31:34PM GMT, Mahadevan wrote:
> Document the DPU for Qualcomm SA8775P platform.
>
> Signed-off-by: Mahadevan
> ---
>
> [v2]
> - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry]
> - Update bindings by fixing dt_binding_check tool errors (update
On Thu, Sep 26, 2024 at 04:31:33PM GMT, Mahadevan wrote:
> Document the MDSS hardware found on the Qualcomm SA8775P platform.
>
> Signed-off-by: Mahadevan
> ---
>
> [v2]
> - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry]
> - Update bindings by fixing dt_binding_check
On Thu, 26 Sep 2024 16:31:33 +0530, Mahadevan wrote:
> Document the MDSS hardware found on the Qualcomm SA8775P platform.
>
> Signed-off-by: Mahadevan
> ---
>
> [v2]
> - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry]
> - Update bindings by fixing dt_binding_check to
On Thu, 26 Sep 2024 16:31:34 +0530, Mahadevan wrote:
> Document the DPU for Qualcomm SA8775P platform.
>
> Signed-off-by: Mahadevan
> ---
>
> [v2]
> - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry]
> - Update bindings by fixing dt_binding_check tool errors (update i
On Thu, Sep 26, 2024 at 04:31:35PM GMT, Mahadevan wrote:
> Add Mobile Display Subsystem (MDSS) support for the SA8775P platform.
>
> Signed-off-by: Mahadevan
> ---
>
> [v2]
> - Update commit message. [Dmitry]
> - Reorder compatible string of MDSS based on alphabetical order. [Dmitry]
> - add reg
On Thu, Sep 26, 2024 at 04:31:33PM +0530, Mahadevan wrote:
> Document the MDSS hardware found on the Qualcomm SA8775P platform.
>
> Signed-off-by: Mahadevan
> ---
>
> [v2]
> - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry]
> - Update bindings by fixing dt_binding_chec
On Thu, Sep 26, 2024 at 04:55:02PM GMT, Mahadevan P wrote:
> Sorry, Please ignore this thread/coverletter
>
go/upstream and adopt b4, please.
On Thu, Sep 26, 2024 at 04:31:36PM GMT, Mahadevan wrote:
> Add definitions for the display hardware used on the
> Qualcomm SA8775P platform.
>
> Signed-off-by: Mahadevan
> ---
Reviewed-by: Dmitry Baryshkov
Minor nit below.
> [v2]
> - Reorder compatible string of DPU based on alphabetical orde
On Thu, Sep 26, 2024 at 04:31:37PM GMT, Mahadevan wrote:
> Add mdss0 and mdp devicetree nodes for sa8775p target.
>
> Signed-off-by: Mahadevan
>
> ---
>
> This patch depends on the clock enablement change:
> https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/
>
>
Sorry, Please ignore this thread/coverletter
On 9/26/2024 4:33 PM, Mahadevan wrote:
This series introduces support to enable the Mobile Display Subsystem (MDSS)
and Display Processing Unit (DPU) for the Qualcomm SA8775P target. It
includes the addition of the hardware catalog, compatible string,
On 26/09/2024 13:01, Mahadevan wrote:
> Document the DPU for Qualcomm SA8775P platform.
>
> Signed-off-by: Mahadevan
> ---
>
> [v2]
> - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry]
> - Update bindings by fixing dt_binding_check tool errors (update includes in
> exa
On 26/09/2024 13:01, Mahadevan wrote:
> +
> + clocks:
> +items:
> + - description: Display AHB
> + - description: Display hf AXI
> + - description: Display core
> +
> + iommus:
> +maxItems: 1
> +
> + interconnects:
> +maxItems: 3
> +
> + interconnect-names:
> +max
On Fri, Sep 13, 2024 at 12:51:31PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
> devices (x1-85, possibly others), it seems to pass that barrier while
> there are still things in the event completion FIFO waiting to be
> written
From: Rob Clark
The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
devices (x1-85, possibly others), it seems to pass that barrier while
there are still things in the event completion FIFO waiting to be
written back to memory.
Work around that by adding a fence wait before contex
Add missing bitfields to CONTEXT_SWITCH_CNTL in a6xx.xml.
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8450-HDK
Signed-off-by: Antonino Maniscalco
---
drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 7 ++-
1 file chan
On 9/26/2024 6:32 PM, Dmitry Baryshkov wrote:
On Thu, Sep 26, 2024 at 04:31:35PM GMT, Mahadevan wrote:
Add Mobile Display Subsystem (MDSS) support for the SA8775P platform.
Signed-off-by: Mahadevan
---
[v2]
- Update commit message. [Dmitry]
- Reorder compatible string of MDSS based on alpha
This patch implements preemption feature for A6xx targets, this allows
the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
hardware as such supports multiple levels of preemption granularities,
ranging from coarse grained(ringbuffer level) to a more fine grained
such as draw-cal
This series implements preemption for A7XX targets, which allows the GPU to
switch to an higher priority ring when work is pushed to it, reducing latency
for high priority submissions.
This series enables L1 preemption with skip_save_restore which requires
the following userspace patches to functi
The bv_fence field of rbmemptrs was being used incorrectly as the BV
rptr shadow pointer in some places.
Add a bv_rptr field and change the code to use that instead.
Reviewed-by: Akhil P Oommen
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil
Initialize with 4 rings to enable preemption.
For now only on a750 as other targets require testing.
Add the "preemption_enabled" module parameter to override this for other
a7xx targets.
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstr
Use the postamble to reset perf counters when switching between rings,
except when sysprof is enabled, analogously to how they are reset
between submissions when switching pagetables.
Reviewed-by: Akhil P Oommen
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8550-QRD
Some userspace changes are necessary so add a flag for userspace to
advertise support for preemption when creating the submitqueue.
When this flag is not set preemption will not be allowed in the middle
of the submitted IBs therefore mantaining compatibility with older
userspace.
The flag is reje
Add documentation about the preemption feature supported by the msm
driver.
Signed-off-by: Antonino Maniscalco
---
Documentation/gpu/msm-preemption.rst | 99
1 file changed, 99 insertions(+)
diff --git a/Documentation/gpu/msm-preemption.rst
b/Documentation/
In mesa CP_SET_CTXSWITCH_IB is renamed to CP_SET_AMBLE and some other
names are changed to match KGSL. Import those changes.
The changes have not been merged yet in mesa but are necessary for this
series.
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8550-QRD
Tested
With preemption it is not enough to track the current_ctx_seqno globally
as execution might switch between rings.
This is especially problematic when current_ctx_seqno is used to
determine whether a page table switch is necessary as it might lead to
security bugs.
Track current context per ring.
Adds a field to `adreno_info` to store the GPU specific preempt record
size.
Reviewed-by: Akhil P Oommen
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8450-HDK
Signed-off-by: Antonino Maniscalco
---
drivers/gpu/drm/msm/ad
Add trace points corresponding to preemption being triggered and being
completed for latency measurement purposes.
Reviewed-by: Akhil P Oommen
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8450-HDK
Signed-off-by: Antonino M
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