On Thu, 05 Sep 2024 06:08:20 +0300, Dmitry Baryshkov wrote:
> Add two selects for DRM_DISPLAY_DSC_HELPER which got missed in the
> original commit ca097d4d94d8 ("drm/display: split DSC helpers from DP
> helpers") and were later reported by LKP.
>
>
Applied to misc/kernel.git (drm-misc-next).
Th
On Thu, 5 Sept 2024 at 10:48, Maxime Ripard wrote:
>
> On Thu, 05 Sep 2024 06:08:20 +0300, Dmitry Baryshkov wrote:
> > Add two selects for DRM_DISPLAY_DSC_HELPER which got missed in the
> > original commit ca097d4d94d8 ("drm/display: split DSC helpers from DP
> > helpers") and were later reported
From: Rob Clark
This reverts commit 85b715a334583488ad7fbd3001fe6fd617b7d4c0.
It was causing gpu smmu faults on x1e80100.
I _think_ what is causing this is the change in ordering of
__arm_lpae_clear_pte() (dma_sync_single_for_device() on the pgtable
memory) and io_pgtable_tlb_flush_walk(). I'm
On 05/09/2024 1:49 pm, Rob Clark wrote:
From: Rob Clark
This reverts commit 85b715a334583488ad7fbd3001fe6fd617b7d4c0.
It was causing gpu smmu faults on x1e80100.
I _think_ what is causing this is the change in ordering of
__arm_lpae_clear_pte() (dma_sync_single_for_device() on the pgtable
mem
On Tue, Sep 03, 2024 at 06:04:13PM GMT, Jessica Zhang wrote:
>
>
> On 8/30/2024 3:16 PM, Dmitry Baryshkov wrote:
> > On Fri, 30 Aug 2024 at 22:28, Jessica Zhang
> > wrote:
> > >
> > >
> > >
> > > On 8/30/2024 10:18 AM, Dmitry Baryshkov wrote:
> > > > On Thu, Aug 29, 2024 at 01:48:32PM GMT, J
On 05/09/2024 2:24 pm, Robin Murphy wrote:
On 05/09/2024 1:49 pm, Rob Clark wrote:
From: Rob Clark
This reverts commit 85b715a334583488ad7fbd3001fe6fd617b7d4c0.
It was causing gpu smmu faults on x1e80100.
I _think_ what is causing this is the change in ordering of
__arm_lpae_clear_pte() (dma
On Thu, Sep 5, 2024 at 6:24 AM Robin Murphy wrote:
>
> On 05/09/2024 1:49 pm, Rob Clark wrote:
> > From: Rob Clark
> >
> > This reverts commit 85b715a334583488ad7fbd3001fe6fd617b7d4c0.
> >
> > It was causing gpu smmu faults on x1e80100.
> >
> > I _think_ what is causing this is the change in orde
This series implements preemption for A7XX targets, which allows the GPU to
switch to an higher priority ring when work is pushed to it, reducing latency
for high priority submissions.
This series enables L1 preemption with skip_save_restore which requires
the following userspace patches to functi
The bv_fence field of rbmemptrs was being used incorrectly as the BV
rptr shadow pointer in some places.
Add a bv_rptr field and change the code to use that instead.
Signed-off-by: Antonino Maniscalco
Reviewed-by: Akhil P Oommen
Tested-by: Neil Armstrong # on SM8650-QRD
---
drivers/gpu/drm/ms
Adds a field to `adreno_info` to store the GPU specific preempt record
size.
Signed-off-by: Antonino Maniscalco
Reviewed-by: Akhil P Oommen
Tested-by: Neil Armstrong # on SM8650-QRD
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 4
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
2 files
Add missing bitfields to CONTEXT_SWITCH_CNTL in a6xx.xml.
Signed-off-by: Antonino Maniscalco
---
drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
b/drivers/gpu/drm/msm/registers/
This patch implements preemption feature for A6xx targets, this allows
the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
hardware as such supports multiple levels of preemption granularities,
ranging from coarse grained(ringbuffer level) to a more fine grained
such as draw-cal
In mesa CP_SET_CTXSWITCH_IB is renamed to CP_SET_AMBLE and some other
names are changed to match KGSL. Import those changes.
The changes have not been merged yet in mesa but are necessary for this
series.
Signed-off-by: Antonino Maniscalco
---
.../gpu/drm/msm/registers/adreno/adreno_pm4.xml
Use the postamble to reset perf counters when switching between rings,
except when sysprof is enabled, analogously to how they are reset
between submissions when switching pagetables.
Signed-off-by: Antonino Maniscalco
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 20 ++-
drive
Add trace points corresponding to preemption being triggered and being
completed for latency measurement purposes.
Signed-off-by: Antonino Maniscalco
Tested-by: Neil Armstrong # on SM8650-QRD
---
drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 7 +++
drivers/gpu/drm/msm/msm_gpu_trace.h |
Some userspace changes are necessary so add a flag for userspace to
advertise support for preemption when creating the submitqueue.
When this flag is not set preemption will not be allowed in the middle
of the submitted IBs therefore mantaining compatibility with older
userspace.
The flag is reje
Initialize with 4 rings to enable preemption.
For now only on A750 as other targets require testing.
Add the "preemption_enabled" module parameter to override this for other
A7xx targets.
Signed-off-by: Antonino Maniscalco
Tested-by: Neil Armstrong # on SM8650-QRD
---
drivers/gpu/drm/msm/adre
Add documentation about the preemption feature supported by the msm
driver.
Signed-off-by: Antonino Maniscalco
---
Documentation/gpu/msm-preemption.rst | 98
1 file changed, 98 insertions(+)
diff --git a/Documentation/gpu/msm-preemption.rst
b/Documentation/
Hi Rob,
On Thu, Sep 05, 2024 at 05:49:56AM -0700, Rob Clark wrote:
> From: Rob Clark
>
> This reverts commit 85b715a334583488ad7fbd3001fe6fd617b7d4c0.
>
> It was causing gpu smmu faults on x1e80100.
>
> I _think_ what is causing this is the change in ordering of
> __arm_lpae_clear_pte() (dma_s
On 05/09/2024 05:33, Dmitry Baryshkov wrote:
> On Wed, 24 Jul 2024 17:01:33 +0200, Marc Gonzalez wrote:
>
>> DT bits required for HDMI TX support in qcom APQ8098 (MSM8998 cousin)
>
> Applied, thanks!
>
> [1/6] dt-bindings: phy: add qcom,hdmi-phy-8998
> https://gitlab.freedesktop.org/lumag/
On 05/09/2024 2:57 pm, Rob Clark wrote:
On Thu, Sep 5, 2024 at 6:24 AM Robin Murphy wrote:
On 05/09/2024 1:49 pm, Rob Clark wrote:
From: Rob Clark
This reverts commit 85b715a334583488ad7fbd3001fe6fd617b7d4c0.
It was causing gpu smmu faults on x1e80100.
I _think_ what is causing this is th
On 05/09/2024 4:53 pm, Will Deacon wrote:
Hi Rob,
On Thu, Sep 05, 2024 at 05:49:56AM -0700, Rob Clark wrote:
From: Rob Clark
This reverts commit 85b715a334583488ad7fbd3001fe6fd617b7d4c0.
It was causing gpu smmu faults on x1e80100.
I _think_ what is causing this is the change in ordering of
On Thu, Sep 5, 2024 at 9:27 AM Robin Murphy wrote:
>
> On 05/09/2024 4:53 pm, Will Deacon wrote:
> > Hi Rob,
> >
> > On Thu, Sep 05, 2024 at 05:49:56AM -0700, Rob Clark wrote:
> >> From: Rob Clark
> >>
> >> This reverts commit 85b715a334583488ad7fbd3001fe6fd617b7d4c0.
> >>
> >> It was causing gpu
On Thu, Sep 5, 2024 at 10:00 AM Rob Clark wrote:
>
> On Thu, Sep 5, 2024 at 9:27 AM Robin Murphy wrote:
> >
> > On 05/09/2024 4:53 pm, Will Deacon wrote:
> > > Hi Rob,
> > >
> > > On Thu, Sep 05, 2024 at 05:49:56AM -0700, Rob Clark wrote:
> > >> From: Rob Clark
> > >>
> > >> This reverts commit
In certain use-cases, a CRTC could switch between two encoders
and because the mode being programmed on the CRTC remains
the same during this switch, the CRTC's mode_changed remains false.
In such cases, the encoder's mode_set also gets skipped.
Skipping mode_set on the encoder for such cases coul
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