[PATCH v2 0/3] drm/msm: Further expose UBWC tiling parameters

After testing, there are more parameters that we're programming which affect how UBWC tiles are laid out in memory and therefore affect the Mesa implementation of VK_EXT_host_image_copy [1], which includes a CPU implementation of tiling and detiling images. In particular we have: 1. ubwc_mode, whi

[PATCH v2 1/3] drm/msm: Update a6xx register XML

Update to Mesa commit 81fd13913a97 ("freedreno: Fix RBBM_NC_MODE_CNTL variants"). Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 1617 - 1 file changed, 1603 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/registers/adren

[PATCH v2 2/3] drm/msm: Expand UBWC config setting

According to downstream we should be setting RBBM_NC_MODE_CNTL to a non-default value on a663 and a680, we don't support a663 and on a680 we're leaving it at the wrong (suboptimal) value. Just set it on all GPUs. Similarly, plumb through level2_swizzling_dis which will be necessary on a663. ubwc_m

[PATCH v2 3/3] drm/msm: Expose expanded UBWC config uapi

This adds extra parameters that affect UBWC tiling that will be used by the Mesa implementation of VK_EXT_host_image_copy. Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++ include/uapi/drm/msm_drm.h | 2 ++ 2 files changed, 8 insertions(+) diff -