On 08/11/2023 16:58, Laurent Pinchart wrote:
On Wed, Nov 08, 2023 at 04:34:39PM +0100, Maxime Ripard wrote:
On Tue, Nov 07, 2023 at 04:26:34PM +0100, Greg Kroah-Hartman wrote:
On Tue, Nov 07, 2023 at 01:18:14PM +0100, Maxime Ripard wrote:
On Tue, Nov 07, 2023 at 12:22:21PM +0100, Greg Kroah-Ha
This series brings:
- interconnect plumbing
- display setup
for QCM2290/QRB2210 and
- CAN bus controller
- HDMI display
- wifi fw variant name
for QTI RB1
and the necessary bindings changes
Patch 1-2 is for Dmitry/freedreno
Patch 3 for Georgi/icc
Patch 5 for Will/iommu
the rest are for Bjorn/q
The "qcom,dsi-ctrl-6g-qcm2290" has been deprecated in commit 0c0f65c6dd44
("dt-bindings: msm: dsi-controller-main: Add compatible strings for every
current SoC"), but the example hasn't been updated to reflect that.
Fix that.
Fixes: 0c0f65c6dd44 ("dt-bindings: msm: dsi-controller-main: Add compat
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there are
other connection paths:
- a path that connects rotator block to the DDR.
- a path that needs to be handled to ensure MDSS register access
functions properly, namely the "reg bus", a.k.a the CPU-MDSS CFG
interconnect.
Describ
Every Qualcomm SoC physically has a "CRYPTO0<->DDR" interconnect lane.
Allow this property to be present, no matter the SoC.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 15 ---
1 file changed, 15 deleti
Add the QCM2290 MDSS compatible to clients compatible list, as it also
needs the workarounds.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
MDSS, aside from the MDP-MEM path, also requires the CPU-DISP_CFG one.
Failing to provide it may result in register accesses failing and that's
never good.
Add the missing path.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++--
1 file changed, 6 insertions(+),
QCM2290 has a single BWMONv4 intance for CPU. Document it.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/interconnect
MDSS, aside from the MDP-MEM path, also requires the CPU-DISP_CFG one.
Failing to provide it may result in register accesses failing and that's
never good.
Add the missing path.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++--
1 file changed, 7 insertions(+),
Add the required nodes to support display on QCM2290.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/qcm2290.dtsi | 214 ++
1 file changed, 214 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
b/arch/arm6
Add interconnect provider nodes and hook up interconnects to consumer
devices, including bwmon.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/qcm2290.dtsi | 248 ++
1 file changed, 248 insertions(+)
diff --git a/arch/arm
Add the required nodes to support display output via the HDMI port.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 86
1 file changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.
Enable the Microchip mcp2518fd hosted on the SPI5 bus.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts
b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts
index
From: Dmitry Baryshkov
The RB1 platform doesn't have board-specific board-id programmed, it uses
generic 0xff. Thus add the property with the 'variant' of the
calibration data.
Note: the driver will check for the calibration data for the following
IDs, so existing board-2.bin files will continue
On 15.07.2023 17:25, Konrad Dybcio wrote:
> On 11.07.2023 18:31, Dmitry Baryshkov wrote:
>> On 11/07/2023 17:21, Dmitry Baryshkov wrote:
>>>
>>> On Tue, 20 Jun 2023 13:43:19 +0200, Konrad Dybcio wrote:
Some recent SoCs use power rails that we model as GENPDs to power the
DSIPHY. This seri
On 11/28/2023 12:24 PM, Dmitry Baryshkov wrote:
On Tue, 28 Nov 2023 at 19:43, Paloma Arellano wrote:
On 11/27/2023 5:48 PM, Dmitry Baryshkov wrote:
On Tue, 28 Nov 2023 at 03:12, Paloma Arellano wrote:
Trigger a devcoredump to dump dpu registers and capture the drm atomic
state when the fr
The is_connected flag is set to true after DP mainlink successfully
finishes link training to enter into ST_MAINLINK_READY state rather
than being set after the DP dongle is connected. Rename the
is_connected flag with link_ready flag to match the state of DP
driver's state machine.
Changes in v5:
The purpose of this patch series is to incorporate pm runtime framework
into MSM eDP/DP driver so that eDP panel can be detected by DRM eDP panel
driver during system probe time. During incorporating procedure, original
customized pm realted fucntions, such as dp_pm_prepare(), dp_pm_suspend(),
dp_p
Currently the dp_display_request_irq() is executed at
msm_dp_modeset_init() which ties irq registering to the DPU device's
life cycle, while depending on resources that are released as the DP
device is torn down. Move register DP driver irq handler to
dp_display_probe() to have dp_display_irq_handl
EV_HPD_INIT_SETUP flag is used to trigger the initialization of external
DP host controller. Since external DP host controller initialization had
been incorporated into pm_runtime_resume(), this flag became obsolete.
msm_dp_irq_postinstall() which triggers EV_HPD_INIT_SETUP event is
obsoleted accor
Currently DP driver is executed independent of PM runtime framework.
This leads msm eDP panel can not being detected by edp_panel driver
during generic_edp_panel_probe() due to AUX DPCD read failed at
edp panel driver. Incorporate PM runtime framework into DP driver so
that host controller's power
Currently DP driver use drm_helper_hpd_irq_event(), bypassing drm bridge
framework, to report HPD status changes to user space frame work.
Replace it with drm_bridge_hpd_notify() since DP driver is part of drm
bridge.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm
Original both parser->parse() and dp_power_client_init() are done at
dp_display_bind() since eDP population is done at binding time.
In the preparation of having eDP population done at probe() time,
move both function from dp_display_bind() to dp_display_probe().
Changes in v6:
-- move dp_power_cl
Currently eDP population is done at msm_dp_modeset_init() which happen
at binding time. Move eDP population to be done at display probe time
so that probe deferral cases can be handled effectively.
wait_for_hpd_asserted callback is added during drm_dp_aux_init()
to ensure eDP's HPD is up before pro
Trigger a devcoredump to dump dpu registers and capture the drm atomic
state when the frame_done_timer timeouts.
Signed-off-by: Paloma Arellano
---
Changes since v1:
- Optimized the format in which frame_done_timeout_cnt is incremented
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 12 +
A DCE (Display Compression Engine) contains two DSC hard slice encoders.
Each DCE start with even DSC encoder index followed by an odd DSC encoder
index. Each encoder can work independently. But Only two DSC encoders from
same DCE can be paired to work together to support merge mode. In addition,
t
On Wed, 29 Nov 2023 at 22:31, Kuogee Hsieh wrote:
>
> A DCE (Display Compression Engine) contains two DSC hard slice encoders.
> Each DCE start with even DSC encoder index followed by an odd DSC encoder
> index. Each encoder can work independently. But Only two DSC encoders from
> same DCE can be
On Wed, 29 Nov 2023 at 20:42, Paloma Arellano wrote:
>
> Trigger a devcoredump to dump dpu registers and capture the drm atomic
> state when the frame_done_timer timeouts.
>
> Signed-off-by: Paloma Arellano
> ---
>
> Changes since v1:
> - Optimized the format in which frame_done_timeout_cnt is in
On Wed, 29 Nov 2023 at 19:47, Kuogee Hsieh wrote:
>
> Currently DP driver is executed independent of PM runtime framework.
> This leads msm eDP panel can not being detected by edp_panel driver
> during generic_edp_panel_probe() due to AUX DPCD read failed at
> edp panel driver. Incorporate PM runt
On Sat, 28 Oct 2023 at 01:33, Jessica Zhang wrote:
>
> Document and add support for solid_fill property to drm_plane. In
> addition, add support for setting and getting the values for solid_fill.
>
> To enable solid fill planes, userspace must assign a property blob to
> the "solid_fill" plane pro
On Sat, 28 Oct 2023 at 01:33, Jessica Zhang wrote:
>
> Loosen the requirements for atomic and legacy commit so that, in cases
> where pixel_source != FB, the commit can still go through.
>
> This includes adding framebuffer NULL checks in other areas to account for
> FB being NULL when non-FB pixe
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