Le jeu. 20 avr. 2023 à 01:10, Dmitry Baryshkov
a écrit :
>
> On 19/04/2023 17:41, Arnaud Vrac wrote:
> > Now that cursor sspp blocks can be used for cursor planes, enable them
> > on msm8998. The dma sspp blocks that were assigned to cursor planes can
> > now be used for overlay planes instead.
>
Le jeu. 20 avr. 2023 à 01:18, Dmitry Baryshkov
a écrit :
>
> On 19/04/2023 17:41, Arnaud Vrac wrote:
> > This avoids using lm blocks that support DSPP when not needed, to
> > keep those resources available.
>
> This will break some of the platforms. Consider qcm2290 which has a
> single LM with DS
Le jeu. 20 avr. 2023 à 02:20, Dmitry Baryshkov
a écrit :
>
> On 18/04/2023 21:10, Arnaud Vrac wrote:
> > Some Qualcomm SoCs that support HDMI also support CEC, including MSM8996
> > and MSM8998. The hardware block can handle a single CEC logical address
> > and broadcast messages.
> >
> > Port the
Le jeu. 20 avr. 2023 à 00:43, Dmitry Baryshkov
a écrit :
>
> On 19/04/2023 17:41, Arnaud Vrac wrote:
> > The dpu backend already handles applying alpha to the base stage, so we
> > can use it to render the bottom plane in all cases. This allows mixing
> > one additional plane with the hardware mix
16
(https://download.01.org/0day-ci/archive/20230420/202304201512.cllnzi0u-...@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/
On Thu, 20 Apr 2023 at 10:06, Arnaud Vrac wrote:
>
> Le jeu. 20 avr. 2023 à 01:10, Dmitry Baryshkov
> a écrit :
> >
> > On 19/04/2023 17:41, Arnaud Vrac wrote:
> > > Now that cursor sspp blocks can be used for cursor planes, enable them
> > > on msm8998. The dma sspp blocks that were assigned to
On Thu, 20 Apr 2023 at 10:24, Arnaud Vrac wrote:
>
> Le jeu. 20 avr. 2023 à 02:20, Dmitry Baryshkov
> a écrit :
> >
> > On 18/04/2023 21:10, Arnaud Vrac wrote:
> > > Some Qualcomm SoCs that support HDMI also support CEC, including MSM8996
> > > and MSM8998. The hardware block can handle a single
On 20/04/2023 10:26, Arnaud Vrac wrote:
Le jeu. 20 avr. 2023 à 00:43, Dmitry Baryshkov
a écrit :
On 19/04/2023 17:41, Arnaud Vrac wrote:
The dpu backend already handles applying alpha to the base stage, so we
can use it to render the bottom plane in all cases. This allows mixing
one additiona
16
(https://download.01.org/0day-ci/archive/20230420/202304201909.d57x63j5-...@intel.com/config)
compiler: ia64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/
On 20/04/2023 04:14, Konrad Dybcio wrote:
SDM845 was the first SoC to include both PCC v4 and GC v1.8.
We don't currently support any other blocks but the common config
for these two can be reused for a large amount of SoCs.
Rename it to indicate the origin of that combo.
Signed-off-by: Konrad
On 20/04/2023 04:14, Konrad Dybcio wrote:
SDM845 was the first SoC to include both PCC v4 and GC v1.8.
We don't currently support any other blocks but the common config
for these two can be reused for a large amount of SoCs.
Rename it to indicate the origin of that combo.
Signed-off-by: Konrad
On 11/04/2023 17:31, Jianhua Lu wrote:
This fixes warning:
sm8250-xiaomi-elish-csot.dtb: dsi@ae94000: Unevaluated properties are not
allowed ('qcom,master-dsi', 'qcom,sync-dual-dsi' were unexpected)
Signed-off-by: Jianhua Lu
---
.../bindings/display/msm/dsi-controller-main.yaml| 12 ++
On 13/04/2023 01:42, Rob Clark wrote:
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.c | 11 +--
drivers/gpu/drm/msm/msm_gpu.c | 2 --
2 files changed, 5 insertions(+), 8 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On 15/04/2023 02:02, Marijn Suijten wrote:
On 2023-04-14 09:46:17, Kuogee Hsieh wrote:
In current code, the dsc active bits are set only if the cfg->dsc is set.
This is the old sentence from v1 again, did you accidentally send the
wrong patch as the improvements from v2 are missing?
However,
On 18/04/2023 02:14, Marijn Suijten wrote:
The WB debug log mask ended up never being assigned, leading to writes
to this block to never be logged even if the mask is enabled in
dpu_hw_util_log_mask via sysfs.
Fixes: 84a33d0fd921 ("drm/msm/dpu: add dpu_hw_wb abstraction for writeback
blocks")
S
On 18/04/2023 02:14, Marijn Suijten wrote:
Some of these members were initialized while never read, while others
were not even assigned any value at all. Drop them to save some space,
and above all confusion when looking at these members.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
On 18/04/2023 02:14, Marijn Suijten wrote:
The Resource Manager already iterates over all available blocks from the
catalog, only to pass their ID to a dpu_hw_xxx_init() function which
uses an _xxx_offset() helper to search for and find the exact same
catalog pointer again to initialize the block
On 18/04/2023 19:41, Rob Clark wrote:
From: Rob Clark
For a similar reason as commit f2c7ca890182 ("drm/atomic-helper: Don't
set deadline for modesets"), we need the crtc to be already active in
order to compute a target vblank time for an async commit. Otherwise
we get this splat reminding us
On 4/18/2023 9:41 AM, Rob Clark wrote:
From: Rob Clark
For a similar reason as commit f2c7ca890182 ("drm/atomic-helper: Don't
set deadline for modesets"), we need the crtc to be already active in
order to compute a target vblank time for an async commit. Otherwise
we get this splat remindin
On 4/20/2023 7:33 AM, Dmitry Baryshkov wrote:
On 18/04/2023 02:14, Marijn Suijten wrote:
Some of these members were initialized while never read, while others
were not even assigned any value at all. Drop them to save some space,
and above all confusion when looking at these members.
Fixes:
Hi Dmitry / Marijn
On 4/20/2023 7:03 AM, Dmitry Baryshkov wrote:
On 15/04/2023 02:02, Marijn Suijten wrote:
On 2023-04-14 09:46:17, Kuogee Hsieh wrote:
In current code, the dsc active bits are set only if the cfg->dsc is
set.
This is the old sentence from v1 again, did you accidentally send
On 20/04/2023 19:40, Abhinav Kumar wrote:
Hi Dmitry / Marijn
On 4/20/2023 7:03 AM, Dmitry Baryshkov wrote:
On 15/04/2023 02:02, Marijn Suijten wrote:
On 2023-04-14 09:46:17, Kuogee Hsieh wrote:
In current code, the dsc active bits are set only if the cfg->dsc is
set.
This is the old sentenc
On 4/19/2023 3:23 PM, Dmitry Baryshkov wrote:
On 19/04/2023 17:41, Arnaud Vrac wrote:
This avoids using two LMs instead of one when the display width is lower
than the maximum supported value. For example on MSM8996/MSM8998, the
actual maxwidth is 2560, so we would use two LMs for 1280x720 or
On 4/19/2023 7:41 AM, Arnaud Vrac wrote:
Do not override the hsync/vsync polarity passed by the encoder when
setting up intf timings. The same logic was used in both the encoder and
intf code to set the DP and DSI polarities, so those interfaces are not
impacted. However for HDMI, the polariti
On 20/04/2023 04:36, Konrad Dybcio wrote:
On 20.04.2023 03:28, Abhinav Kumar wrote:
On 4/19/2023 6:26 PM, Konrad Dybcio wrote:
On 20.04.2023 03:25, Dmitry Baryshkov wrote:
On 20/04/2023 04:14, Konrad Dybcio wrote:
Almost all SoCs from SDM845 to SM8550 inclusive feature a GC1.8
dspp sub-
On Thu, 20 Apr 2023 at 21:01, Jeykumar Sankaran
wrote:
>
>
>
> On 4/19/2023 7:41 AM, Arnaud Vrac wrote:
> > Do not override the hsync/vsync polarity passed by the encoder when
> > setting up intf timings. The same logic was used in both the encoder and
> > intf code to set the DP and DSI polaritie
On 4/20/2023 11:01 AM, Dmitry Baryshkov wrote:
On 20/04/2023 04:36, Konrad Dybcio wrote:
On 20.04.2023 03:28, Abhinav Kumar wrote:
On 4/19/2023 6:26 PM, Konrad Dybcio wrote:
On 20.04.2023 03:25, Dmitry Baryshkov wrote:
On 20/04/2023 04:14, Konrad Dybcio wrote:
Almost all SoCs from S
On 2023-04-20 21:01:04, Dmitry Baryshkov wrote:
> On 20/04/2023 04:36, Konrad Dybcio wrote:
> >
> >
> > On 20.04.2023 03:28, Abhinav Kumar wrote:
> >>
> >>
> >> On 4/19/2023 6:26 PM, Konrad Dybcio wrote:
> >>>
> >>>
> >>> On 20.04.2023 03:25, Dmitry Baryshkov wrote:
> On 20/04/2023 04:14, Ko
On 20/04/2023 22:47, Abhinav Kumar wrote:
On 4/20/2023 11:01 AM, Dmitry Baryshkov wrote:
On 20/04/2023 04:36, Konrad Dybcio wrote:
On 20.04.2023 03:28, Abhinav Kumar wrote:
On 4/19/2023 6:26 PM, Konrad Dybcio wrote:
On 20.04.2023 03:25, Dmitry Baryshkov wrote:
On 20/04/2023 04:14, Ko
On 4/20/2023 12:51 PM, Dmitry Baryshkov wrote:
On 20/04/2023 22:47, Abhinav Kumar wrote:
On 4/20/2023 11:01 AM, Dmitry Baryshkov wrote:
On 20/04/2023 04:36, Konrad Dybcio wrote:
On 20.04.2023 03:28, Abhinav Kumar wrote:
On 4/19/2023 6:26 PM, Konrad Dybcio wrote:
On 20.04.2023 03:2
On 2023-04-20 22:51:22, Dmitry Baryshkov wrote:
> On 20/04/2023 22:47, Abhinav Kumar wrote:
> >
> >
> > On 4/20/2023 11:01 AM, Dmitry Baryshkov wrote:
> >> On 20/04/2023 04:36, Konrad Dybcio wrote:
> >>>
> >>>
> >>> On 20.04.2023 03:28, Abhinav Kumar wrote:
>
>
> On 4/19/2023 6:26
The regdma is currently not used by the current driver. We have no way
to practically verify that the regdma is described correctly. Drop it
now.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 2 -
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 2 -
.../ms
On 20/04/2023 22:53, Abhinav Kumar wrote:
On 4/20/2023 12:51 PM, Dmitry Baryshkov wrote:
On 20/04/2023 22:47, Abhinav Kumar wrote:
On 4/20/2023 11:01 AM, Dmitry Baryshkov wrote:
On 20/04/2023 04:36, Konrad Dybcio wrote:
On 20.04.2023 03:28, Abhinav Kumar wrote:
On 4/19/2023 6:26 PM,
On 2023-04-20 08:46:46, Abhinav Kumar wrote:
>
>
> On 4/20/2023 7:33 AM, Dmitry Baryshkov wrote:
> > On 18/04/2023 02:14, Marijn Suijten wrote:
> >> Some of these members were initialized while never read, while others
> >> were not even assigned any value at all. Drop them to save some space,
>
On 2023-04-20 03:47:57, Dmitry Baryshkov wrote:
> On 17/04/2023 23:21, Marijn Suijten wrote:
> > A bunch of registers were appended at the end in e.g. 91143873a05d
> > ("drm/msm/dpu: Add MISR register support for interface") rather than
> > being inserted in a place that maintains numerical sorting
On 2023-04-20 04:03:31, Dmitry Baryshkov wrote:
[..]
> >>> -static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp,
> >>> +static void dpu_hw_setup_vsync_source_v1(struct dpu_hw_mdp *mdp,
> >>> struct dpu_vsync_source_cfg *cfg)
> >>
> >> In my opinion _v1 is not really descripti
On 2023-04-20 04:11:29, Dmitry Baryshkov wrote:
> On 17/04/2023 23:21, Marijn Suijten wrote:
> > All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of
> > the PINGPONG block and into the INTF block. Wire up these interrupts
> > and IRQ masks on all supported hardware.
> >
> > Si
Whoops, looks like I wrongly lost all the cc's when importing b4-am's
mbx file which is just a patch with a few but not all email headers.
Cc'ing everyone on this occasion with my review.
On 2023-04-20 23:33:07, Marijn Suijten wrote:
> On 2023-04-20 23:07:42, Dmitry Baryshkov wrote:
> > The regdma
On 21/04/2023 00:39, Marijn Suijten wrote:
On 2023-04-20 08:46:46, Abhinav Kumar wrote:
On 4/20/2023 7:33 AM, Dmitry Baryshkov wrote:
On 18/04/2023 02:14, Marijn Suijten wrote:
Some of these members were initialized while never read, while others
were not even assigned any value at all. Dro
The regdma is currently not used by the current driver. We have no way
to practically verify that the regdma is described correctly. Drop it
now.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 -
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 2 -
.../ms
Stop mapping the regdma region. The driver does not support regdma.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 --
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 +-
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/
On 21/04/2023 01:01, Marijn Suijten wrote:
Whoops, looks like I wrongly lost all the cc's when importing b4-am's
mbx file which is just a patch with a few but not all email headers.
Cc'ing everyone on this occasion with my review.
On 2023-04-20 23:33:07, Marijn Suijten wrote:
On 2023-04-20 23:0
On 21/04/2023 00:51, Marijn Suijten wrote:
On 2023-04-20 04:03:31, Dmitry Baryshkov wrote:
[..]
-static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp,
+static void dpu_hw_setup_vsync_source_v1(struct dpu_hw_mdp *mdp,
struct dpu_vsync_source_cfg *cfg)
In my opinion _v1 i
Add the DSI host found on SM6350.
Acked-by: Rob Herring
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
b/Docume
v1 -> v2:
- Rebase on the DPU catalog rework and INTF_TE
- Fix QSEED(3L/4) discrepancies
- Fixed DMA/cursor discrepancies for 6350
- No deduplication, that's gonna be handled in catalogrework 2:
"the return of the catalogrework"
- Split MDSS & DPU binding additions
- Drop "Allow variable SSPP/INT
Document the SM6350 MDSS.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +
1 file changed, 214 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
b/Documentation/devicetree/bindings/dis
Add the DSI host found on SM6375.
Acked-by: Rob Herring
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
b/Docume
Document the SM6350 DPU.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++
1 file changed, 94 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
b/Documentation/devicetree/bindings/display
Document the SM6375 MDSS.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +
1 file changed, 216 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
b/Documentation/devicetree/bindings/dis
Add support for MDSS on SM6350.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e8c93731aaa1..4e3a5f0c303c 100644
--- a/drivers/gpu/drm/msm/msm_mdss.
Add basic SM6375 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |
Document SM6375 DPU.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6375-dpu.yaml | 106 +
1 file changed, 106 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml
b/Documentation/devicetree/bindings/display/ms
From: Konrad Dybcio
Add the SM6350 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-sm
Add SM6350 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1
It got broken at some point, fix it up.
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 2daaa600ac75.
Add the SM6375 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm
Add support for MDSS on SM6375.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 4e3a5f0c303c..f2470ce699f7 100644
--- a/drivers/gpu/drm/msm/msm_md
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add SM6350 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalo
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add support for MDSS on SM6350.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 9 +
1 file changed, 9 insertions(+)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add basic SM6375 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +
driver
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add support for MDSS on SM6375.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 10 ++
1 file changed, 10 insertions(+)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add support for MDSS on SM6375.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 4e3a5f0c303c..f2470c
On 21/04/2023 01:31, Konrad Dybcio wrote:
From: Konrad Dybcio
Add the SM6350 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 inser
On 20/04/2023 22:56, Marijn Suijten wrote:
On 2023-04-20 22:51:22, Dmitry Baryshkov wrote:
On 20/04/2023 22:47, Abhinav Kumar wrote:
On 4/20/2023 11:01 AM, Dmitry Baryshkov wrote:
On 20/04/2023 04:36, Konrad Dybcio wrote:
On 20.04.2023 03:28, Abhinav Kumar wrote:
On 4/19/2023 6:26 PM,
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add the SM6375 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
Acked-by: Dmitry Baryshkov
--
With best
On 21/04/2023 01:31, Konrad Dybcio wrote:
It got broken at some point, fix it up.
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
This should probably come before patches 11 and 12.
diff --git a/driver
On 21.04.2023 00:41, Dmitry Baryshkov wrote:
> On 21/04/2023 01:31, Konrad Dybcio wrote:
>> Add SM6350 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio
>> Signed-off-by: Konrad Dybcio
>> ---
[...]
>> +
>> +static const struct dpu_sspp_cfg sm6350_sspp[] =
On 21/04/2023 02:05, Konrad Dybcio wrote:
On 21.04.2023 00:41, Dmitry Baryshkov wrote:
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add SM6350 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
---
[...]
+
+static const struct dpu
On 21.04.2023 00:50, Dmitry Baryshkov wrote:
> On 21/04/2023 01:31, Konrad Dybcio wrote:
>> Add support for MDSS on SM6375.
>>
>> Signed-off-by: Konrad Dybcio
>> ---
>> drivers/gpu/drm/msm/msm_mdss.c | 10 ++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
Abhinav Kumar (1):
drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets
Kuogee Hsieh (4):
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separate DSC flush away from dpu_hw_ctl_intf_cfg_v1() by
adding dpu_hw_ctl_update_pending_flush_dsc_v1() to handle both per
DSC engine and DSC flush bits at same time to make it consistent with
the location of flush p
At current implementation, topology configuration is thrown away after
dpu_rm_reserve(). This patch save the topology so that it can be used
for DSC related calculation later.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 32 ++---
1 file c
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary
sub-block and feature flag information.
Each display compression engine (DCE) contains dual hard
slice DSC encoders so both share same base address but with
its own different sub block address.
Signed-off-by: Abhinav K
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 38 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 17 +-
During DSC preparation, add run time calculation to figure out what
usage modes, split mode and merge mode, is going to be setup.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 56 -
1 file changed, 32 insertions(+), 24 deletions(-)
dif
On 21/04/2023 02:25, Kuogee Hsieh wrote:
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 38 ++-
drivers/gpu
On 21/04/2023 02:25, Kuogee Hsieh wrote:
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separate DSC flush away from dpu_hw_ctl_intf_cfg_v1() by
adding dpu_hw_ctl_update_pending_flush_dsc_v1() to handle both per
DSC engine and DSC flush bits at same time to make
On 21/04/2023 02:25, Kuogee Hsieh wrote:
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary
sub-block and feature flag information.
Each display compression engine (DCE) contains dual hard
slice DSC encoders so both share same base address but with
its own different s
On 21/04/2023 02:25, Kuogee Hsieh wrote:
At current implementation, topology configuration is thrown away after
dpu_rm_reserve(). This patch save the topology so that it can be used
for DSC related calculation later.
Please take a look at
https://patchwork.freedesktop.org/patch/527960/?series=
On 21/04/2023 02:25, Kuogee Hsieh wrote:
During DSC preparation, add run time calculation to figure out what
usage modes, split mode and merge mode, is going to be setup.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 56 -
1 file ch
On 4/20/2023 5:12 PM, Dmitry Baryshkov wrote:
On 21/04/2023 02:25, Kuogee Hsieh wrote:
At current implementation, topology configuration is thrown away after
dpu_rm_reserve(). This patch save the topology so that it can be used
for DSC related calculation later.
Please take a look at
https
Hi Kuogee,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm/drm-next drm-exynos/exynos-drm-next
drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip
linus/master v6.3-rc7 next-20230420
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