Hi Rob,
On Thu, 6 Apr 2023 14:59:16 -0700
Rob Clark wrote:
> From: Rob Clark
>
> Add a helper to dump memory stats to fdinfo. For the things the drm
> core isn't aware of, use a callback.
>
> Signed-off-by: Rob Clark
> ---
> Documentation/gpu/drm-usage-stats.rst | 21 +++
> drivers/gp
On Mon, Apr 10, 2023 at 07:50:50AM -0700, Rob Clark wrote:
> Hi Dave,
>
> This is the main pull for v6.4, see below for description. A bit big
> this time because of (1) generated header updates and (2) dpu hw
> catelog rework which split the increasingly unwieldy
> big-giant-file-of-tables into
On Mon, Apr 10, 2023 at 02:06:06PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> Add a helper to dump memory stats to fdinfo. For the things the drm
> core isn't aware of, use a callback.
>
> v2: Fix typos, change size units to match docs, use div_u64
>
> Signed-off-by: Rob Clark
> Reviewed-b
On 11/04/2023 03:57, Abhinav Kumar wrote:
On 4/7/2023 5:27 PM, Dmitry Baryshkov wrote:
On sm8450 platform the CTL_0 doesn't differ from the rest of CTL blocks,
so switch it to CTL_SC7280_MASK too.
Some background: original commit 100d7ef6995d ("drm/msm/dpu: add support
for SM8450") had all (r
On Tue, Apr 11, 2023 at 3:27 AM Daniel Vetter wrote:
>
> On Mon, Apr 10, 2023 at 07:50:50AM -0700, Rob Clark wrote:
> > Hi Dave,
> >
> > This is the main pull for v6.4, see below for description. A bit big
> > this time because of (1) generated header updates and (2) dpu hw
> > catelog rework whi
On Tue, Apr 11, 2023 at 07:55:33AM -0700, Rob Clark wrote:
> On Tue, Apr 11, 2023 at 3:27 AM Daniel Vetter wrote:
> > > Konrad Dybcio (18):
> > > drm/msm/adreno: Use OPP for every GPU generation
> >
> > This had a minor conflict with refactoring from drm-misc-next, I went
> > what's in your
On Tue, Apr 11, 2023 at 3:43 AM Daniel Vetter wrote:
>
> On Mon, Apr 10, 2023 at 02:06:06PM -0700, Rob Clark wrote:
> > From: Rob Clark
> >
> > Add a helper to dump memory stats to fdinfo. For the things the drm
> > core isn't aware of, use a callback.
> >
> > v2: Fix typos, change size units to
On Tue, Apr 11, 2023 at 08:02:09AM -0700, Rob Clark wrote:
> On Tue, Apr 11, 2023 at 3:43 AM Daniel Vetter wrote:
> >
> > On Mon, Apr 10, 2023 at 02:06:06PM -0700, Rob Clark wrote:
> > > From: Rob Clark
> > >
> > > Add a helper to dump memory stats to fdinfo. For the things the drm
> > > core is
On Tue, Apr 11, 2023 at 8:00 AM Daniel Vetter wrote:
>
> On Tue, Apr 11, 2023 at 07:55:33AM -0700, Rob Clark wrote:
> > On Tue, Apr 11, 2023 at 3:27 AM Daniel Vetter wrote:
> > > > Konrad Dybcio (18):
> > > > drm/msm/adreno: Use OPP for every GPU generation
> > >
> > > This had a minor conf
This fixes warning:
sm8250-xiaomi-elish-csot.dtb: dsi@ae94000: Unevaluated properties are not
allowed ('qcom,master-dsi', 'qcom,sync-dual-dsi' were unexpected)
Signed-off-by: Jianhua Lu
---
.../bindings/display/msm/dsi-controller-main.yaml| 12
1 file changed, 12 insertions(+
All adreno_is_*() functions do not modify their argument in any way, so
they can be changed to accept const struct adreno_gpu pointer.
Suggested-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 56 -
1 file changed, 28 insert
The commit 010c8bbad2cb ("drm: msm: adreno: Disable preemption on Adreno
510") tried to check GPU's revn before revn being set. Add WARN_ON_ONCE
to prevent such bugs from happening again. A separate helper is
necessary so that the warning is displayed really just once instead of
being displayed for
On 11/04/2023 19:38, Markus Elfring wrote:
Date: Tue, 11 Apr 2023 18:24:24 +0200
The address of a data structure member was determined before
a corresponding null pointer check in the implementation of
the functions “dpu_hw_pp_enable_te” and “dpu_hw_pp_get_vsync_info”.
Thus avoid the risk for u
On 4/11/2023 9:38 AM, Markus Elfring wrote:
Date: Tue, 11 Apr 2023 18:24:24 +0200
The address of a data structure member was determined before
a corresponding null pointer check in the implementation of
the functions “dpu_hw_pp_enable_te” and “dpu_hw_pp_get_vsync_info”.
Thus avoid the risk f
On Mon, Apr 10, 2023 at 2:06 PM Rob Clark wrote:
>
> From: Rob Clark
>
> Similar motivation to other similar recent attempt[1]. But with an
> attempt to have some shared code for this. As well as documentation.
>
> It is probably a bit UMA-centric, I guess devices with VRAM might want
> some pl
On Tue, Apr 11, 2023 at 09:47:32AM -0700, Rob Clark wrote:
> On Mon, Apr 10, 2023 at 2:06 PM Rob Clark wrote:
> >
> > From: Rob Clark
> >
> > Similar motivation to other similar recent attempt[1]. But with an
> > attempt to have some shared code for this. As well as documentation.
> >
> > It is
On Tue, Apr 11, 2023 at 9:53 AM Daniel Vetter wrote:
>
> On Tue, Apr 11, 2023 at 09:47:32AM -0700, Rob Clark wrote:
> > On Mon, Apr 10, 2023 at 2:06 PM Rob Clark wrote:
> > >
> > > From: Rob Clark
> > >
> > > Similar motivation to other similar recent attempt[1]. But with an
> > > attempt to ha
On Tue, 11 Apr 2023 at 20:13, Rob Clark wrote:
>
> On Tue, Apr 11, 2023 at 9:53 AM Daniel Vetter wrote:
> >
> > On Tue, Apr 11, 2023 at 09:47:32AM -0700, Rob Clark wrote:
> > > On Mon, Apr 10, 2023 at 2:06 PM Rob Clark wrote:
> > > >
> > > > From: Rob Clark
> > > >
> > > > Similar motivation to
On Tue, Apr 11, 2023 at 08:35:48PM +0300, Dmitry Baryshkov wrote:
> On Tue, 11 Apr 2023 at 20:13, Rob Clark wrote:
> >
> > On Tue, Apr 11, 2023 at 9:53 AM Daniel Vetter wrote:
> > >
> > > On Tue, Apr 11, 2023 at 09:47:32AM -0700, Rob Clark wrote:
> > > > On Mon, Apr 10, 2023 at 2:06 PM Rob Clark
On Tue, Apr 11, 2023 at 10:36 AM Dmitry Baryshkov
wrote:
>
> On Tue, 11 Apr 2023 at 20:13, Rob Clark wrote:
> >
> > On Tue, Apr 11, 2023 at 9:53 AM Daniel Vetter wrote:
> > >
> > > On Tue, Apr 11, 2023 at 09:47:32AM -0700, Rob Clark wrote:
> > > > On Mon, Apr 10, 2023 at 2:06 PM Rob Clark wrote
Quoting Dmitry Baryshkov (2023-04-11 09:19:02)
> The commit 010c8bbad2cb ("drm: msm: adreno: Disable preemption on Adreno
> 510") tried to check GPU's revn before revn being set. Add WARN_ON_ONCE
> to prevent such bugs from happening again. A separate helper is
> necessary so that the warning is di
Quoting Dmitry Baryshkov (2023-04-11 09:19:03)
> All adreno_is_*() functions do not modify their argument in any way, so
> they can be changed to accept const struct adreno_gpu pointer.
>
> Suggested-by: Stephen Boyd
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Stephen Boyd
Hi all,
This is v7 of the HDCP patches. The patches are authored by Sean Paul.
I rebased and addressed the review comments in v6-v9.
Main change in v9 is renaming i915 priv data and moving the display type
specific init to the drm helper instead of the driver.
Patches 1-4 focus on moving the co
From: Sean Paul
Move the hdcp atomic check from i915 to drm_hdcp so other
drivers can use it. No functional changes, just cleaned up some of the
code when moving it over.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Sean Paul
Signed-off-by: Mar
From: Sean Paul
Instead of forcing a modeset in the hdcp atomic check, rename to
drm_hdcp_has_changed and return true if the content protection value
is changing and let the driver decide whether a modeset is required or not.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Signed-off-by: Sean
From: Sean Paul
Update the connector's property value in 2 cases which were
previously missed:
1- Content type changes. The value should revert back to DESIRED from
ENABLED in case the driver must re-authenticate the link due to the
new content type.
2- Userspace sets value to DESIRED whi
From: Sean Paul
Stick all of the setup for HDCP into a dedicated function. No functional
change, but this will facilitate moving HDCP logic into helpers.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Signed-off-by: Sean Paul
---
Changes in v2:
-None
Changes in v3:
-None
Changes in v4:
-Non
From: Sean Paul
Expand upon the HDCP helper library to manage HDCP enable, disable, and check.
Previous to this patch, the majority of the state management and sink
interaction is tucked inside the Intel driver with the understanding
that once a new platform supported HDCP we could make good dec
From: Sean Paul
The shim functions return error codes, but they are discarded in
intel_hdcp.c. This patch plumbs the return codes through so they are
properly handled.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Reviewed-by: Suraj Kandpal
Signed-off-by: Sean Paul
Signed-off-by: Mark Yaco
From: Sean Paul
Now that all of the HDCP 1.x logic has been migrated to the central HDCP
helpers, use it in the i915 driver.
The majority of the driver code for HDCP 1.x will live in intel_hdcp.c,
however there are a few helper hooks which are connector-specific and
need to be partially or fully
From: Sean Paul
Add the bindings for the MSM DisplayPort HDCP registers
which are required to write the HDCP key into the display controller as
well as the registers to enable HDCP authentication/key
exchange/encryption.
Cc: Rob Herring
Cc: Stephen Boyd
Reviewed-by: Rob Herring
Reviewed-by: D
From: Sean Paul
Add the register ranges required for HDCP key injection and
HDCP TrustZone interaction as described in the dt-bindings for the
sc7180 dp controller.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Douglas Anderson
Signed-off-by: Sean Paul
Signed-off-by: Mark Yacoub
---
Changes in
From: Sean Paul
Add HDCP 1.x support to msm DP bridges using the new HDCP
helpers.
Cc: Stephen Boyd
Reviewed-by: Stephen Boyd
Signed-off-by: Sean Paul
Signed-off-by: Mark Yacoub
---
Changes in v2:
-Squash [1] into this patch with the following changes (Stephen)
-Update the sc7180 dtsi fi
In current code, the dsc active bits are set only if the cfg->dsc is set.
However, for displays which are hot-pluggable, there can be a use-case
of disconnecting a DSC supported sink and connecting a non-DSC sink.
For those cases we need to clear DSC active bits during teardown.
Fixes: ede3c6bb00
Perform DSC range checking to make sure correct DSC is requested before
reserve resource for it.
Fixes: c985d7bb64ff ("drm/msm/disp/dpu1: Add DSC support in RM")
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
On 4/11/2023 2:09 PM, Kuogee Hsieh wrote:
Perform DSC range checking to make sure correct DSC is requested before
reserve resource for it.
Fixes: c985d7bb64ff ("drm/msm/disp/dpu1: Add DSC support in RM")
I cannot find any fixes tag with this hash.
This is the right one.
Fixes: f2803ee91a4
On 4/11/2023 2:04 PM, Kuogee Hsieh wrote:
In current code, the dsc active bits are set only if the cfg->dsc is set.
However, for displays which are hot-pluggable, there can be a use-case
of disconnecting a DSC supported sink and connecting a non-DSC sink.
For those cases we need to clear DSC
Full-caps DSC in the title, as discussed previously.
On that note, don't forget to CC those who have reviewed your patches
previously, as also brought up in earlier review.
On 2023-04-11 14:04:55, Kuogee Hsieh wrote:
> In current code, the dsc active bits are set only if the cfg->dsc is set.
Som
On 12/04/2023 00:04, Kuogee Hsieh wrote:
In current code, the dsc active bits are set only if the cfg->dsc is set.
However, for displays which are hot-pluggable, there can be a use-case
of disconnecting a DSC supported sink and connecting a non-DSC sink.
For those cases we need to clear DSC acti
On 12/04/2023 00:09, Kuogee Hsieh wrote:
Perform DSC range checking to make sure correct DSC is requested before
reserve resource for it.
Fixes: c985d7bb64ff ("drm/msm/disp/dpu1: Add DSC support in RM")
$ git log -p -1 c985d7bb64ff
fatal: ambiguous argument 'c985d7bb64ff': unknown revision or
Again, don't forget to include previous reviewers in cc, please :)
On 2023-04-11 14:09:40, Kuogee Hsieh wrote:
> Perform DSC range checking to make sure correct DSC is requested before
> reserve resource for it.
This isn't performing any range checking for resource reservations /
requests: this i
On 11/04/2023 21:26, Daniel Vetter wrote:
On Tue, Apr 11, 2023 at 08:35:48PM +0300, Dmitry Baryshkov wrote:
On Tue, 11 Apr 2023 at 20:13, Rob Clark wrote:
On Tue, Apr 11, 2023 at 9:53 AM Daniel Vetter wrote:
On Tue, Apr 11, 2023 at 09:47:32AM -0700, Rob Clark wrote:
On Mon, Apr 10, 2023 a
Hi Marijn
On 4/11/2023 3:24 PM, Marijn Suijten wrote:
Again, don't forget to include previous reviewers in cc, please :)
On 2023-04-11 14:09:40, Kuogee Hsieh wrote:
Perform DSC range checking to make sure correct DSC is requested before
reserve resource for it.
This isn't performing any rang
On 11/04/2023 21:28, Rob Clark wrote:
On Tue, Apr 11, 2023 at 10:36 AM Dmitry Baryshkov
wrote:
On Tue, 11 Apr 2023 at 20:13, Rob Clark wrote:
On Tue, Apr 11, 2023 at 9:53 AM Daniel Vetter wrote:
On Tue, Apr 11, 2023 at 09:47:32AM -0700, Rob Clark wrote:
On Mon, Apr 10, 2023 at 2:06 PM R
As I get more and more active in the drm/msm space, yet sometimes miss
out on patches (where I was involved in previous discussions), add
myself as reviewer to make this involvement clear.
Signed-off-by: Marijn Suijten
---
Note that this is only a slight commitment from my part to look at
patche
On 12/04/2023 01:43, Marijn Suijten wrote:
As I get more and more active in the drm/msm space, yet sometimes miss
out on patches (where I was involved in previous discussions), add
myself as reviewer to make this involvement clear.
Signed-off-by: Marijn Suijten
---
Note that this is only a sli
From: Rob Clark
Similar motivation to other similar recent attempt[1]. But with an
attempt to have some shared code for this. As well as documentation.
It is probably a bit UMA-centric, I guess devices with VRAM might want
some placement stats as well. But this seems like a reasonable start.
From: Rob Clark
Handle a bit of the boiler-plate in a single case, and make it easier to
add some core tracked stats.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_file.c | 39 ++
include/drm/drm_drv.h | 7 +++
include/drm/drm_file.h | 4 ++
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.c | 11 +--
drivers/gpu/drm/msm/msm_gpu.c | 2 --
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 5a10d28de9dd..e516a3544505 10064
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 16 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h | 2 +-
3 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/i915/i915_driver.c | 3 ++-
drivers/gpu/drm/i915/i915_drm_client.c | 18 +-
drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
3 files changed, 8 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915
From: Rob Clark
Add support to dump GEM stats to fdinfo.
v2: Fix typos, change size units to match docs, use div_u64
v3: Do it in core
Signed-off-by: Rob Clark
Reviewed-by: Emil Velikov
---
Documentation/gpu/drm-usage-stats.rst | 21
drivers/gpu/drm/drm_file.c| 76 ++
From: Rob Clark
Use the new helper to export stats about memory usage.
v2: Drop unintended hunk
v3: Rebase
Signed-off-by: Rob Clark
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/msm/msm_gem.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index 44ca803237a5..17d6af94 100644
--- a/drivers/
Hi Mark,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-intel/for-linux-next-fixes]
[also build test WARNING on drm/drm-next linus/master v6.3-rc6 next-20230411]
[cannot apply to drm-tip/drm-tip drm-misc/drm-misc-next
drm-intel/for-linux-next]
[If your
On 4/11/2023 3:17 PM, Dmitry Baryshkov wrote:
On 12/04/2023 00:04, Kuogee Hsieh wrote:
In current code, the dsc active bits are set only if the cfg->dsc is set.
However, for displays which are hot-pluggable, there can be a use-case
of disconnecting a DSC supported sink and connecting a non-DS
On 12/04/2023 02:32, Abhinav Kumar wrote:
On 4/11/2023 3:17 PM, Dmitry Baryshkov wrote:
On 12/04/2023 00:04, Kuogee Hsieh wrote:
In current code, the dsc active bits are set only if the cfg->dsc is
set.
However, for displays which are hot-pluggable, there can be a use-case
of disconnecting a
On 4/11/2023 3:14 PM, Marijn Suijten wrote:
Full-caps DSC in the title, as discussed previously.
On that note, don't forget to CC those who have reviewed your patches
previously, as also brought up in earlier review.
On 2023-04-11 14:04:55, Kuogee Hsieh wrote:
In current code, the dsc activ
On 12/04/2023 01:32, Abhinav Kumar wrote:
Hi Marijn
On 4/11/2023 3:24 PM, Marijn Suijten wrote:
Again, don't forget to include previous reviewers in cc, please :)
On 2023-04-11 14:09:40, Kuogee Hsieh wrote:
Perform DSC range checking to make sure correct DSC is requested before
reserve resour
On 4/11/2023 6:06 PM, Dmitry Baryshkov wrote:
On 12/04/2023 01:32, Abhinav Kumar wrote:
Hi Marijn
On 4/11/2023 3:24 PM, Marijn Suijten wrote:
Again, don't forget to include previous reviewers in cc, please :)
On 2023-04-11 14:09:40, Kuogee Hsieh wrote:
Perform DSC range checking to make s
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