On 5/26/2022 5:07 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-05-26 10:26:18)
During display resolution changes display have to be disabled first
followed by display enable with new resolution. This patch force
main link always be retrained during display enable procedure to
simplify im
During display resolution changes display have to be disabled first
followed by display enabling with new resolution. At current
implementation, display enable function manually kicks up
irq_hpd_handle which will read panel link status and start link
training if link status is not in sync state. Ho
On Fri, 27 May 2022 at 19:08, Kuogee Hsieh wrote:
>
> During display resolution changes display have to be disabled first
> followed by display enabling with new resolution. At current
> implementation, display enable function manually kicks up
> irq_hpd_handle which will read panel link status an
From: Rob Clark
Previously the BO_PINNED state in the submit was tracking two related
but different things: (1) that the buffer object was pinned, and (2)
that the vma (mapping within a set of pagetables) was pinned. But with
fenced vma unpin (needed so that userspace couldn't race with retire
p
Refactor existing CRC code for layer mixer and add CRC support for interface
blocks
Jessica Zhang (3):
drm/msm/dpu: Separate LM-specific CRC code from generic CRC code
drm/msm/dpu: Add MISR register support for interface
drm/msm/dpu: Add interface support for CRC debugfs
drivers/gpu/drm/m
Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
helper method. This way, we can make it easier to get CRCs from other HW
blocks by adding other get_crc helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 72 +++-
Add support for setting MISR registers within the interface
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 55 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 8 ++-
2 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/d
Add support for writing CRC values for the interface block to
the debugfs by calling the necessary MISR setup/collect methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 43 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h| 3 +
drivers/gpu/drm/ms
On 27/05/2022 21:54, Jessica Zhang wrote:
Add support for setting MISR registers within the interface
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 55 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 8 ++-
2 files changed, 61 insertions
On 27/05/2022 21:54, Jessica Zhang wrote:
Add support for writing CRC values for the interface block to
the debugfs by calling the necessary MISR setup/collect methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 43 ++-
drivers/gpu/drm/msm/disp
On 27/05/2022 21:54, Jessica Zhang wrote:
Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
helper method. This way, we can make it easier to get CRCs from other HW
blocks by adding other get_crc helper methods.
Signed-off-by: Jessica Zhang
Reviewed-by: Dmitry Baryshkov
On 2022-05-27 22:38:24, Dmitry Baryshkov wrote:
> [..]
> > #define INTF_CFG2_DATABUS_WIDEN BIT(0)
> > #define INTF_CFG2_DATA_HCTL_ENBIT(4)
> >
> > +#define INTF_MISR_CTRL 0x180
> > +#define INTF_MISR_SIGNATURE0x184
> > +#define INTF_MISR_FRAME_COUNT_
On 5/27/2022 12:38 PM, Dmitry Baryshkov wrote:
On 27/05/2022 21:54, Jessica Zhang wrote:
Add support for setting MISR registers within the interface
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 55 -
drivers/gpu/drm/msm/disp/dpu1/dpu_
During display resolution changes display have to be disabled first
followed by display enabling with new resolution. Display disable
will turn off both pixel clock and main link clock so that main link
have to be re trained during display enable to have new video stream
flow again. At current impl
On 5/27/2022 12:46 PM, Dmitry Baryshkov wrote:
On 27/05/2022 21:54, Jessica Zhang wrote:
Add support for writing CRC values for the interface block to
the debugfs by calling the necessary MISR setup/collect methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
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