On 2022-03-28 13:55, Jonathan Marek wrote:
This matches the implementation of iommu_map_sgtable() used for the
non-per-process page tables path.
This works around the dma_map_sgtable() call (used to invalidate cache)
overwriting sgt->nents with 1 (which is probably a separate issue).
FWIW that
On Mon, 4 Apr 2022 at 23:53, Doug Anderson wrote:
>
> Hi,
>
> On Sat, Apr 2, 2022 at 1:26 PM Dmitry Baryshkov
> wrote:
> >
> > On Sat, 2 Apr 2022 at 20:06, Doug Anderson wrote:
> > >
> > > Hi,
> > >
> > > On Sat, Apr 2, 2022 at 3:37 AM Dmitry Baryshkov
> > > wrote:
> > > >
> > > > On 01/04/2022
Check if the dpu format is supported or not using dpu_find_format.
Co-developed-by: Kalyan Thota
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 22 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++---
2
Changes in RFC:
- Rebase changes to the latest code base.
- Append rotation config variables with v2 and
remove unused variables.(Dmitry)
- Move pixel_ext setup separately from scaler3 config.(Dmitry)
- Add 270 degree rotation to supported rotation list.(Dmitry)
Changes in V2:
- Remove unused macr
- Some DPU versions support inline rot90. It is supported only for
limited amount of UBWC formats.
- There are two versions of inline rotators, v1 (present on sm8250 and
sm7250) and v2 (sc7280). These versions differ in the list of supported
formats and in the scaler possibilities.
Co-developed-by
On Tue, 5 Apr 2022 at 16:41, Vinod Polimera wrote:
>
> Check if the dpu format is supported or not using dpu_find_format.
>
> Co-developed-by: Kalyan Thota
> Signed-off-by: Kalyan Thota
> Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_f
On Tue, 5 Apr 2022 at 16:41, Vinod Polimera wrote:
>
> - Some DPU versions support inline rot90. It is supported only for
> limited amount of UBWC formats.
> - There are two versions of inline rotators, v1 (present on sm8250 and
> sm7250) and v2 (sc7280). These versions differ in the list of suppo
On Mon, 4 Apr 2022 at 19:35, Vinod Koul wrote:
>
> Update headers from mesa commit:
>
> commit 28ae397be111c37c6ced397e12d453a7695701bd
> Author: Vinod Koul
> Date: Fri Apr 1 16:53:04 2022 +0530
>
> freedreno/registers: update dsi registers to support dsc
>
> Display Stream co
On Mon, 4 Apr 2022 at 19:35, Vinod Koul wrote:
>
> When DSC is enabled, we need to configure DSI registers accordingly and
> configure the respective stream compression registers.
>
> Add support to calculate the register setting based on DSC params and
> timing information and configure these reg
Even if some IOMMU has registered itself on the platform "bus", that
doesn't necessarily mean it provides translation for the device we
care about. Replace iommu_present() with a more appropriate check.
Signed-off-by: Robin Murphy
---
drivers/gpu/drm/msm/msm_drv.c | 2 +-
1 file changed, 1 inser
On 4/1/2022 4:11 PM, Dmitry Baryshkov wrote:
As noticed by Dan ([1] an the followup thread) there are multiple issues
with the return values for MSM DSI command transmission callback. In
the error case it can easily return a positive value when it should
have returned a proper error code.
Thi
Hi Rob and Abhinav,
On Mon, Apr 04, 2022 at 11:43:37AM -0700, Rob Clark wrote:
> On Fri, Apr 1, 2022 at 8:38 AM Laurent Pinchart wrote:
> > On Thu, Mar 31, 2022 at 05:12:13PM -0700, Abhinav Kumar wrote:
> > > For some vendor driver implementations, display hardware can
> > > be shared between the
Hi Laurent
On 4/5/2022 9:47 AM, Laurent Pinchart wrote:
Hi Rob and Abhinav,
On Mon, Apr 04, 2022 at 11:43:37AM -0700, Rob Clark wrote:
On Fri, Apr 1, 2022 at 8:38 AM Laurent Pinchart wrote:
On Thu, Mar 31, 2022 at 05:12:13PM -0700, Abhinav Kumar wrote:
For some vendor driver implementations,
Hi Abhinav,
On Tue, Apr 05, 2022 at 09:53:57AM -0700, Abhinav Kumar wrote:
> On 4/5/2022 9:47 AM, Laurent Pinchart wrote:
> > On Mon, Apr 04, 2022 at 11:43:37AM -0700, Rob Clark wrote:
> >> On Fri, Apr 1, 2022 at 8:38 AM Laurent Pinchart wrote:
> >>> On Thu, Mar 31, 2022 at 05:12:13PM -0700, Abhin
Hi Laurent
On 4/5/2022 10:02 AM, Laurent Pinchart wrote:
Hi Abhinav,
On Tue, Apr 05, 2022 at 09:53:57AM -0700, Abhinav Kumar wrote:
On 4/5/2022 9:47 AM, Laurent Pinchart wrote:
On Mon, Apr 04, 2022 at 11:43:37AM -0700, Rob Clark wrote:
On Fri, Apr 1, 2022 at 8:38 AM Laurent Pinchart wrote:
Hi,
On Tue, Apr 5, 2022 at 5:54 AM Dmitry Baryshkov
wrote:
> > 3. For DP and eDP HPD means something a little different. Essentially
> > there are two concepts: a) is a display physically connected and b) is
> > the display powered up and ready. For DP, the two are really tied
> > together. From
On 05/04/2022 20:02, Doug Anderson wrote:
Hi,
On Tue, Apr 5, 2022 at 5:54 AM Dmitry Baryshkov
wrote:
3. For DP and eDP HPD means something a little different. Essentially
there are two concepts: a) is a display physically connected and b) is
the display powered up and ready. For DP, the two ar
HPD plugin handle is responsible for setting up main link and depend on
user space frame work to start video stream. Similarly, HPD unplugged
handle is responsible for tearing down main link and depend on user space
frame work to stop video stream. Connect_pending_timeout and disconnect_
pending_ti
Hi,
On Tue, Apr 5, 2022 at 10:36 AM Dmitry Baryshkov
wrote:
>
> On 05/04/2022 20:02, Doug Anderson wrote:
> > Hi,
> >
> > On Tue, Apr 5, 2022 at 5:54 AM Dmitry Baryshkov
> > wrote:
> >>> 3. For DP and eDP HPD means something a little different. Essentially
> >>> there are two concepts: a) is a d
Hi Laurent
On 4/5/2022 10:08 AM, Abhinav Kumar wrote:
Hi Laurent
On 4/5/2022 10:02 AM, Laurent Pinchart wrote:
Hi Abhinav,
On Tue, Apr 05, 2022 at 09:53:57AM -0700, Abhinav Kumar wrote:
On 4/5/2022 9:47 AM, Laurent Pinchart wrote:
On Mon, Apr 04, 2022 at 11:43:37AM -0700, Rob Clark wrote:
Hi Vinod,
I love your patch! Perhaps something to improve:
[auto build test WARNING on 05241de1f69eb7f56b0a5e0bec96a7752fad1b2f]
url:
https://github.com/intel-lab-lkp/linux/commits/Vinod-Koul/drm-msm-Add-Display-Stream-Compression-Support/20220405-003745
base
Quoting Kuogee Hsieh (2022-04-05 11:17:07)
> HPD plugin handle is responsible for setting up main link and depend on
Is "HPD plugin handle" a function? Can you use the function name?
> user space frame work to start video stream. Similarly, HPD unplugged
> handle is responsible for tearing down m
Remove from struct msm_drm_private unused field plane_property.
Fixes: 7d36db0be3b9 ("drm/msm/mdp5: switch to standard zpos property")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_drv.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/g
On 04/04/2022 19:34, Vinod Koul wrote:
When DSC is enabled, we need to configure DSI registers accordingly and
configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and
timing information and configure these registers.
Signed-of
While running the kernel with the mutex debugging enabled, I noticed the
warning reported in the first commit (that the bridge's hpd_mutex is
unitialized). Additional research revealed that we do not add and remove
internal drm_bridges in the msm drm driver. Fix this now.
Dmitry Baryshkov (4):
d
Add calls to drm_bridge_add()/drm_bridge_remove() for the internal HDMI
bridges. This fixes the following warning.
[2.195003] [ cut here ]
[2.195044] WARNING: CPU: 0 PID: 1 at kernel/locking/mutex.c:579
__mutex_lock+0x840/0x9f4
[2.198774] DEBUG_LOCKS_WARN_ON(lo
Add calls to drm_bridge_add()/drm_bridge_remove() for the internal DSI
bridges.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_manager.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 0c
Unwind all drm_bridge_add() calls for internal bridges and remove all
bridges added by the msm driver itself by calling drm_bridge_remove().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_drv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/dr
Add calls to drm_bridge_add()/drm_bridge_remove() for the internal DP
bridges.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_drm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index 80f59cf99089..a7415f
MSM DRM driver stores connectors, encoders and planes in the arrays
inside struct msm_drm_private. They are not really necessary, as
drm_devices also references lists of these objects. Drop private arrays
and use drm_mode_foo() macros.
Note, the crtc array is kept intact as it is used in vblank ha
Remove manual removal of DRM modesetting objects, it is done anyway by
the drm_mode_config_cleanup() called from msm_drm_uninit(). Other
MSM display drivers (MDP4, MDP5) do not manually destroy objects and
trust generic code to do it's work.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/ms
Rather than manually looping over encoders array, use standard
drm_for_each_encoder() macro.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 +++--
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 6 ++
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a
There is no point now in storing arrays of creates planes, connectors
and encoders. Remove them from struct msm_drm_private.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 ++--
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 7 ---
drivers/gpu/drm/msm/
Quoting Dmitry Baryshkov (2022-03-30 15:30:08)
> Make dp_connector_mode_valid() return precise MODE_CLOCK_HIGH rather
> than generic MODE_BAD in case the mode clock is higher than
> DP_MAX_PIXEL_CLK_KHZ (675 MHz).
>
> Signed-off-by: Dmitry Baryshkov
> ---
Suggested-by: Stephen Boyd
Reviewed-by:
Quoting Dmitry Baryshkov (2022-04-05 16:41:21)
> Remove from struct msm_drm_private unused field plane_property.
>
> Fixes: 7d36db0be3b9 ("drm/msm/mdp5: switch to standard zpos property")
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/msm_drv.h | 3 ---
> 1 file changed, 3 deletion
Quoting Dmitry Baryshkov (2022-04-05 16:45:48)
> Add calls to drm_bridge_add()/drm_bridge_remove() for the internal HDMI
> bridges. This fixes the following warning.
>
> [2.195003] [ cut here ]
Usually this line is left out
> [2.195044] WARNING: CPU: 0 PID: 1 at ke
Quoting Dmitry Baryshkov (2022-04-05 16:50:57)
> Remove manual removal of DRM modesetting objects, it is done anyway by
> the drm_mode_config_cleanup() called from msm_drm_uninit(). Other
> MSM display drivers (MDP4, MDP5) do not manually destroy objects and
> trust generic code to do it's work.
>
Quoting Dmitry Baryshkov (2022-04-05 16:50:58)
> Rather than manually looping over encoders array, use standard
> drm_for_each_encoder() macro.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Stephen Boyd
Quoting Dmitry Baryshkov (2022-04-05 16:50:59)
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index d661debb50f1..ee3093890d97 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -184,23 +184,14 @@ struct msm_drm_private {
>
>
On 06-04-22, 02:42, Dmitry Baryshkov wrote:
> On 04/04/2022 19:34, Vinod Koul wrote:
> > When DSC is enabled, we need to configure DSI registers accordingly and
> > configure the respective stream compression registers.
> >
> > Add support to calculate the register setting based on DSC params and
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