revise widebus timing engine programming and enable widebus feature base on chip
Kuogee Hsieh (2):
drm/msm/dpu: revise timing engine programming to support widebus
feature
drm/msm/dp: enable widebus feature for display port
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 14 -
Widebus feature will transmit two pixel data per pixel clock to interface.
Timing engine provides driving force for this purpose. This patch base
on HPG (Hardware Programming Guide) to revise timing engine register
setting to accommodate both widebus and non widebus application. Also
horizontal wid
Widebus feature will transmit two pixel data per pixel clock to interface.
This feature now is required to be enabled to easy migrant to higher
resolution applications in future. However since some legacy chipsets
does not support this feature, this feature is enabled base on chip's
hardware revisi
On Wed, 16 Feb 2022 at 20:34, Kuogee Hsieh wrote:
>
> Widebus feature will transmit two pixel data per pixel clock to interface.
> Timing engine provides driving force for this purpose. This patch base
> on HPG (Hardware Programming Guide) to revise timing engine register
> setting to accommodate
On 2/16/2022 9:48 AM, Dmitry Baryshkov wrote:
On Wed, 16 Feb 2022 at 20:34, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to interface.
Timing engine provides driving force for this purpose. This patch base
on HPG (Hardware Programming Guide) to revise timin
On 2/10/2022 2:34 AM, Vinod Koul wrote:
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
Somehow second patch of this series is not showing up on patchwork in
your REPOST.
Hi,
On Thu, Feb 10, 2022 at 3:58 AM Sankeerth Billakanti
wrote:
>
> Add support for sharp LQ140M1JW46 display panel. It is a 14" eDP panel
> with 1920x1080 display resolution.
>
> Signed-off-by: Sankeerth Billakanti
> Acked-by: Rob Herring
> Reviewed-by: Stephen Boyd
> ---
>
> Changes in v4:
>
Quoting Kuogee Hsieh (2022-01-24 15:17:54)
> Some of DP link compliant test expects to return fail-safe mode
> if prefer detailed timing mode can not be supported by mainlink's
> lane and rate after link training. Therefore add fail-safe mode
> into connector mode list as backup mode. This patch fi
Hi,
On Thu, Feb 10, 2022 at 3:58 AM Sankeerth Billakanti
wrote:
>
> Add support for the 14" sharp,lq140m1jw46 eDP panel.
>
> Signed-off-by: Sankeerth Billakanti
> ---
> 00 ff ff ff ff ff ff 00 4d 10 23 15 00 00 00 00
> 35 1e 01 04 a5 1f 11 78 07 de 50 a3 54 4c 99 26
> 0f 50 54 00 00 00 01 01 01
Hi,
On Wed, Feb 16, 2022 at 11:26 AM Doug Anderson wrote:
>
> Hi,
>
> On Thu, Feb 10, 2022 at 3:58 AM Sankeerth Billakanti
> wrote:
> >
> > Add support for sharp LQ140M1JW46 display panel. It is a 14" eDP panel
> > with 1920x1080 display resolution.
> >
> > Signed-off-by: Sankeerth Billakanti
>
Hi,
On Wed, Feb 16, 2022 at 11:29 AM Doug Anderson wrote:
>
> Hi,
>
> On Thu, Feb 10, 2022 at 3:58 AM Sankeerth Billakanti
> wrote:
> >
> > Add support for the 14" sharp,lq140m1jw46 eDP panel.
> >
> > Signed-off-by: Sankeerth Billakanti
> > ---
> > 00 ff ff ff ff ff ff 00 4d 10 23 15 00 00 00 0
On 2/10/2022 2:34 AM, Vinod Koul wrote:
This adds SDM845 DSC blocks into hw_catalog
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
Reviewed-by: Abhinav Kumar
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 20 +++
1 file changed, 20 insertions(+)
diff --g
On 16/02/2022 21:57, Abhinav Kumar wrote:
On 2/10/2022 2:34 AM, Vinod Koul wrote:
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
Somehow second patch of this series is not
On 2/10/2022 2:34 AM, Vinod Koul wrote:
In SDM845, DSC can be enabled by writing to pingpong block registers, so
add support for DSC in hw_pp
Reviewed-by: Abhinav Kumar
For the sake of uniformity, please use
Reviewed-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod
On 2/10/2022 2:34 AM, Vinod Koul wrote:
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c |
On 2/10/2022 2:34 AM, Vinod Koul wrote:
We need to configure the encoder for DSC configuration and calculate DSC
parameters for the given timing so this patch adds that support by
adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
Signed-off-by: Vinod Koul
Minor nit below,
DPTA_HCTL_EN controls data timing which can be different from
video timing. It only required to be enabled either widebus
or compression enabled.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/dri
Widebus feature will transmit two pixel data per pixel clock to interface.
Timing engine provides driving force for this purpose. This patch base
on HPG (Hardware Programming Guide) to revise timing engine register
setting to accommodate both widebus and non widebus application. Also
horizontal wid
revise widebus timing engine programming and enable widebus feature base on chip
Kuogee Hsieh (4):
drm/msm/dpu: revise timing engine programming to support widebus
feature
drm/msm/dpu: delete DATA_HCTL_EN from sc7280 hw feature
drm/msm/dpu: replace BIT(x) with correspond marco define st
To improve code readability, this patch replace BIT(x) with
correspond register bit define string
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw
Widebus feature will transmit two pixel data per pixel clock to interface.
This feature now is required to be enabled to easy migrant to higher
resolution applications in future. However since some legacy chipsets
does not support this feature, this feature is enabled base on chip's
hardware revisi
Quoting Kuogee Hsieh (2022-02-02 10:56:37)
> DP driver is a generic driver which supports both eDP and DP.
> For debugging purpose it is required to have capabilities to
> differentiate message are generated from eDP or DP. This patch
> add connector type into debug messages for this purpose.
>
> C
Quoting Kuogee Hsieh (2022-02-02 10:56:38)
> DP phy should be initialized and exited symmetrically to avoid
> clock being stucked at either on or off error. Add debug info
> to cover all DP phy to identify clock issues easily.
>
> Signed-off-by: Kuogee Hsieh
> ---
Reviewed-by: Stephen Boyd
Quoting Kuogee Hsieh (2022-02-02 10:56:39)
Please add some commit text
> Signed-off-by: Kuogee Hsieh
> ---
> drivers/gpu/drm/msm/dp/dp_audio.c | 49 +++--
> drivers/gpu/drm/msm/dp/dp_catalog.c | 34 +++-
> drivers/gpu/drm/msm/dp/dp_ctrl.c| 106
> +++-
The dsi_7nm_phy_enable() disagrees with downstream for
glbl_str_swi_cal_sel_ctrl and glbl_hstx_str_ctrl_0 values. Update
programmed settings to match downstream driver. To remove the
possibility for such errors in future drop less_than_1500_mhz
assignment and specify settings explicitly.
Fixes: 5a
On 2/16/2022 3:46 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-02-02 10:56:39)
Please add some commit text
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_audio.c | 49 +++--
drivers/gpu/drm/msm/dp/dp_catalog.c | 34 +++-
drivers/gpu/drm/msm/dp/dp
On 2/16/2022 4:08 PM, Dmitry Baryshkov wrote:
The dsi_7nm_phy_enable() disagrees with downstream for
glbl_str_swi_cal_sel_ctrl and glbl_hstx_str_ctrl_0 values. Update
programmed settings to match downstream driver. To remove the
possibility for such errors in future drop less_than_1500_mhz
ass
On 2/10/2022 2:34 AM, Vinod Koul wrote:
When DSC is enabled, we need to pass the DSC parameters to panel driver
as well, so add a dsc parameter in panel and set it when DSC is enabled
Also, fetch and pass DSC configuration for DSI panels to DPU encoder,
which will enable and configure DSC har
On 17/02/2022 03:22, Kuogee Hsieh wrote:
On 2/16/2022 3:46 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-02-02 10:56:39)
Please add some commit text
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_audio.c | 49 +++--
drivers/gpu/drm/msm/dp/dp_catalog.c | 34
On 16/02/2022 05:35, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2022-01-31 13:05:13)
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h
b/drivers/gpu/drm/msm/dp/dp_parser.h
index 094b39bfed8c..f16072f33cdb 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.h
+++ b/drivers/gpu/drm/msm/dp/dp_parser.h
On 16/02/2022 05:31, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2022-01-31 13:05:12)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 60fe06018581..4d184122d63e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/dr
On 15/02/2022 18:15, Bjorn Andersson wrote:
On Tue 15 Feb 08:44 CST 2022, Dmitry Baryshkov wrote:
On 15/02/2022 07:37, Bjorn Andersson wrote:
It's typical for the bootloader to configure CTL_0 for the boot splash
or EFIFB, but for non-DSI use cases the DPU driver tend to pick another
CTL and t
On 15/02/2022 20:51, Abhinav Kumar wrote:
On 2/15/2022 6:16 AM, Dmitry Baryshkov wrote:
Rather than passing DRM_MODE_ENCODER_* and letting dpu_encoder to guess,
which intf type we mean, pass INTF_DSI/INTF_DP directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_en
On 16/02/2022 05:22, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2022-02-01 07:10:55)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index ff2218155b44..803fd6f25da1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
SC8180x has the eDP controller wired up to INTF_5, so add the interrupt
register block for this interface to the list.
Signed-off-by: Bjorn Andersson
---
Changes since v2:
- None
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 6 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 1
From: Rob Clark
Add SC8180x to the hardware catalog, for initial support for the
platform. Due to limitations in the DP driver only one of the four DP
interfaces is left enabled.
The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and
the Windows-on-Snapdragon bootloader leaves t
On 17/02/2022 04:21, Bjorn Andersson wrote:
From: Rob Clark
Add SC8180x to the hardware catalog, for initial support for the
platform. Due to limitations in the DP driver only one of the four DP
interfaces is left enabled.
The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and
On 2/10/2022 2:34 AM, Vinod Koul wrote:
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when we are using DSC
We add a helper dpu_encoder_helper_get_dsc() to detect dsc
enabled and pass this to .setup_intf_cfg()
Signed
On 2/10/2022 2:34 AM, Vinod Koul wrote:
Somehow documentation for dspp was missed, so add that
Signed-off-by: Vinod Koul
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/msm_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm
On 2/10/2022 2:34 AM, Vinod Koul wrote:
This add the bits in RM to enable the DSC blocks
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
--Reviewed-by: Abhinav Kumar
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 56
On 2/10/2022 2:34 AM, Vinod Koul wrote:
Add a mode valid callback for dsi_mgr for checking mode being valid in
case of DSC. For DSC the height and width needs to be multiple of slice,
so we check that here
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
Reviewed-by: Abhinav Kumar
On 2/10/2022 2:34 AM, Vinod Koul wrote:
This add the bits in RM to enable the DSC blocks
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 56
On 2/10/2022 2:34 AM, Vinod Koul wrote:
When DSC is enabled, we need to configure DSI registers accordingly and
configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and
timing information and configure these registers.
Signe
Remove loops over hw_vbif. Instead always VBIF's idx as an index in the
array. This fixes an error in dpu_kms_hw_init(), where we fill
dpu_kms->hw_vbif[i], but check for an error pointer at
dpu_kms->hw_vbif[vbif_idx].
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Dmitry Ba
Using IS_ERR_OR_NULL() together with PTR_ERR() is a typical mistake. If
the value is NULL, then the function will return 0 instead of a proper
return code. Moreover dpu_hw_vbif_init() function can not return NULL.
So, replace corresponding IS_ERR_OR_NULL() call with IS_ERR().
Signed-off-by: Dmitry
We do not expect to have other VBIFs. Drop VBIF_n indices and always use
VBIF_RT and VBIF_NRT.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 4 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 6 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 36 +
This patchset targets DPU encoder code, removing unused artifacts (empty
callbacks, MSM bus client id, etc).
Changes since v2:
- Expand commit message of 7th patch (pull connector from
dpu_encoder_phys to dpu_encoder_virt)
- Drop intf_type patch for now, as it causes controversy
Changes sinc
The msm_display_info structure is not used by the rest of msm driver, so
move it into the dpu1 (dpu_encoder.h to be precise).
Reviewed-by: Abhinav Kumar
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 18 ++
drivers/gp
We do not use MSM bus client, so drop bus_scaling_client field from
dpu_encoder_virt.
Reviewed-by: Abhinav Kumar
Reviewed-by: Bjorn Andersson
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 --
1 file changed, 2 deletions(-)
diff
DP audio enablement code which is comparing intf_type,
DRM_MODE_ENCODER_TMDS (= 2) with DRM_MODE_CONNECTOR_DisplayPort (= 10).
Which would never succeed. Fix it to check for DRM_MODE_ENCODER_TMDS.
Fixes: d13e36d7d222 ("drm/msm/dp: add audio support for Display Port on MSM")
Reviewed-by: Abhinav Ku
Make dpu_encoder use atomic_mode_set to receive connector and CRTC
states as arguments rather than finding connector and CRTC by manually
looping through the respective lists.
Reviewed-by: Abhinav Kumar
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1
Both cmd and vid backends provide useless mode_fixup() callback. Drop
it.
Reviewed-by: Bjorn Andersson
Reviewed-by: Abhinav Kumar
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 4
drivers/gpu/drm/msm/disp/dpu1/dpu_encod
All physical encoders used by virtual encoder share the same connector,
so pull the connector field from dpu_encoder_phys into dpu_encoder_virt
structure. Otherwise code suggests that different phys_encs
can have different connectors.
Reviewed-by: Abhinav Kumar
Reviewed-by: Stephen Boyd
Signed-o
Stop caching msm_dp instance in dpu_encoder_virt since it's not used
now.
Fixes: 8a3b4c17f863 ("drm/msm/dp: employ bridge mechanism for display enable
and disable")
Reviewed-by: Abhinav Kumar
Reviewed-by: Bjorn Andersson
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/g
On 16/02/2022 04:56, Abhinav Kumar wrote:
On 2/1/2022 7:10 AM, Dmitry Baryshkov wrote:
Remove additional indirection: specify IRQ callbacks and IRQ indices
directly rather than through the pointer in the irq structure. For each
IRQ we have a constant IRQ callback. This change simplifies code r
This is the second part of
https://patchwork.freedesktop.org/series/91631/ reworked and cleaned up.
Changes since v1:
- Use ARRAY_SIZE() rather INTR_IDX_MAX when clearing irq arrays.
Changes since the original pull request:
- Split applied patches
- Add unlikely and WARN_ON in dpu_core_irq_reg
Remove extra dpu_irq_* wrappers from dpu_kms.c, merge them directly into
dpu_core_irq_* functions.
Reviewed-by: Abhinav Kumar
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 12 -
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.
DPU interrupts code allows multiple callbacks per interrut. In reality
none of the interrupts is shared between blocks (and will probably never
be). Drop support for registering multiple callbacks per interrupt to
simplify interrupt handling code.
Reported-by: kernel test robot
Reported-by: kerne
The argument clear of the function dpu_core_irq_read() is always true.
Remove it.
Reviewed-by: Abhinav Kumar
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 4 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +--
driv
Pass IRQ number directly rather than passing an index in the dpu_encoder's irq
table.
Reviewed-by: Stephen Boyd
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 +--
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
Get rid of dpu_encoder_helper_register_irq/unregister_irq helpers, call
dpu_core_register/unregister_callback directly, without surrounding them
with helpers.
Reviewed-by: Abhinav Kumar
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
Remove additional indirection: specify IRQ callbacks and IRQ indices
directly rather than through the pointer in the irq structure. For each
IRQ we have a constant IRQ callback. This change simplifies code review
as the reader no longer needs to remember which function is called.
Signed-off-by: Dm
On 16-02-22, 22:46, Dmitry Baryshkov wrote:
> On 16/02/2022 21:57, Abhinav Kumar wrote:
> >
> >
> > On 2/10/2022 2:34 AM, Vinod Koul wrote:
> > > Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
> > > support by adding hw blocks for DSC
> > >
> > > Reviewed-by: Dmitry Bary
On 16-02-22, 11:49, Abhinav Kumar wrote:
>
>
> On 2/10/2022 2:34 AM, Vinod Koul wrote:
> > In SDM845, DSC can be enabled by writing to pingpong block registers, so
> > add support for DSC in hw_pp
> >
> > Reviewed-by: Abhinav Kumar
>
> For the sake of uniformity, please use
>
> Reviewed-by: A
This is the second part of
https://patchwork.freedesktop.org/series/91631/ reworked and cleaned up.
Changes since v1:
- Fix warning ins dpu_trace.h related to
dpu_core_irq_unregister_callback event
Changes since v1:
- Use ARRAY_SIZE() rather INTR_IDX_MAX when clearing irq arrays.
Changes sin
Remove extra dpu_irq_* wrappers from dpu_kms.c, merge them directly into
dpu_core_irq_* functions.
Reviewed-by: Abhinav Kumar
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 12 -
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.
Remove additional indirection: specify IRQ callbacks and IRQ indices
directly rather than through the pointer in the irq structure. For each
IRQ we have a constant IRQ callback. This change simplifies code review
as the reader no longer needs to remember which function is called.
Signed-off-by: Dm
The argument clear of the function dpu_core_irq_read() is always true.
Remove it.
Reviewed-by: Abhinav Kumar
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 4 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +--
driv
Get rid of dpu_encoder_helper_register_irq/unregister_irq helpers, call
dpu_core_register/unregister_callback directly, without surrounding them
with helpers.
Reviewed-by: Abhinav Kumar
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
DPU interrupts code allows multiple callbacks per interrut. In reality
none of the interrupts is shared between blocks (and will probably never
be). Drop support for registering multiple callbacks per interrupt to
simplify interrupt handling code.
Reported-by: kernel test robot
Signed-off-by: Dmi
Pass IRQ number directly rather than passing an index in the dpu_encoder's irq
table.
Reviewed-by: Stephen Boyd
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 +--
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
msm_dss_clk_*() functions significantly duplicate clk_bulk_* family of
functions. Drop custom code and use bulk clocks directly. This also
removes dependency of DP driver on the DPU driver internals.
Note that DP changes were compile-only tested.
Changes since v4:
- Use size_t for num_clocks in
DPU driver contains code to parse clock items from device tree into
special data struct and then enable/disable/set rate for the clocks
using that data struct. However the DPU driver itself uses only parsing
and enabling/disabling part (the rate setting is used by DP driver).
Move this implementat
"ctrl_link" is the clock from DP_CTRL_PM module. The result of setting
the rate for it would be a call to dev_pm_opp_set_rate(). Instead of
saving the rate inside struct dss_module_power, call the
devm_pm_opp_set_rate() directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_ctrl
The only clock for which we set the rate is the "stream_pixel". Rather
than storing the rate and then setting it by looping over all the
clocks, set the clock rate directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_clk_util.c | 33
drivers/gpu/dr
In order to simplify DP code, drop hand-coded loops over clock arrays,
replacing them with clk_bulk_* functions.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Makefile | 1 -
drivers/gpu/drm/msm/dp/dp_clk_util.c | 87
drivers/gpu/drm/msm/dp/dp_clk_
Inline the dp_power_clk_set_rate() function, replacing it with the call
to msm_dss_enable_clk().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_power.c | 23 ++-
1 file changed, 6 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_power.c
b
On 16-02-22, 11:54, Abhinav Kumar wrote:
> > +/**
> > + * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
> > + * This helper function is used by physical encoder to get DSC blocks
> > mask
> > + * used for this encoder.
>
> This looks slightly misaligned to me or not su
On 16-02-22, 19:11, Abhinav Kumar wrote:
>
>
> On 2/10/2022 2:34 AM, Vinod Koul wrote:
> > We cannot enable mode_3d when we are using the DSC. So pass
> > configuration to detect DSC is enabled and not enable mode_3d
> > when we are using DSC
> >
> > We add a helper dpu_encoder_helper_get_dsc()
On 16-02-22, 19:44, Abhinav Kumar wrote:
>
>
> On 2/10/2022 2:34 AM, Vinod Koul wrote:
> > When DSC is enabled, we need to configure DSI registers accordingly and
> > configure the respective stream compression registers.
> >
> > Add support to calculate the register setting based on DSC params
On 2/16/2022 10:10 PM, Vinod Koul wrote:
On 16-02-22, 19:11, Abhinav Kumar wrote:
On 2/10/2022 2:34 AM, Vinod Koul wrote:
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when we are using DSC
We add a helper dpu_enc
On 17/02/2022 01:05, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to interface.
Timing engine provides driving force for this purpose. This patch base
on HPG (Hardware Programming Guide) to revise timing engine register
setting to accommodate both widebus and n
On 17/02/2022 01:05, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to interface.
This feature now is required to be enabled to easy migrant to higher
resolution applications in future. However since some legacy chipsets
does not support this feature, this featur
On 17/02/2022 01:05, Kuogee Hsieh wrote:
To improve code readability, this patch replace BIT(x) with
correspond register bit define string
Signed-off-by: Kuogee Hsieh
This patch should come first.
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 16 +++-
1 file changed, 11 i
On 17/02/2022 09:33, Abhinav Kumar wrote:
On 2/16/2022 10:10 PM, Vinod Koul wrote:
On 16-02-22, 19:11, Abhinav Kumar wrote:
On 2/10/2022 2:34 AM, Vinod Koul wrote:
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when
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