In the current implementation, substring comparison
using device node name is used to find mdp node
during driver probe. Use compatible string list instead
of node name to get mdp node from the parent mdss node.
Signed-off-by: Krishna Manikandan
Changes in v2:
- Use compatible lists instead of
On Tue, 9 Nov 2021 at 12:47, Krishna Manikandan
wrote:
>
> In the current implementation, substring comparison
> using device node name is used to find mdp node
> during driver probe. Use compatible string list instead
> of node name to get mdp node from the parent mdss node.
>
> Signed-off-by: Kr
On 11/8/2021 4:29 PM, Bjorn Andersson wrote:
On Mon 08 Nov 15:42 PST 2021, Kuogee Hsieh wrote:
From: Kuogee Hsieh
Combo phy supports both USB and DP simultaneously. There may has a
possible conflict during phy initialization phase between USB and
DP driver which may cause USB phy timeout wh
From: Rob Clark
The first patch adds a easy way to write debugfs files (needed to
disable hw fault detection, so we can test the sw timeout fallback).
The second adds some helpers for cmdstream building. And the third
adds the new tests.
Rob Clark (3):
lib/igt_debugfs: Add helper for writing
From: Rob Clark
A pretty minimal subset compared to what a full gallium driver would
need, but OTOH for igt tests we should only need to emit fairly basic
command stream.
Signed-off-by: Rob Clark
---
lib/igt_msm.c | 102 ++
lib/igt_msm.h | 48 ++
From: Rob Clark
Signed-off-by: Rob Clark
---
lib/igt_debugfs.c | 16
lib/igt_debugfs.h | 12
2 files changed, 28 insertions(+)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index a5bb95ca..39431068 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -35
From: Rob Clark
Add tests to exercise:
1. sw hangcheck timeout
2. gpu fault (hang) recovery
3. iova fault recovery
Signed-off-by: Rob Clark
---
lib/igt_msm.h| 3 +
tests/meson.build| 1 +
tests/msm_recovery.c | 172 +++
3 files changed,
If you happened to try to access `/dev/drm_dp_aux` devices provided by
the MSM DP AUX driver too early at bootup you could go boom. Let's
avoid that by only allowing AUX transfers when the controller is
powered up.
Specifically the crash that was seen (on Chrome OS 5.4 tree with
relevant backports
From: Rob Clark
This started out as conversion to using drm/sched to handle job timeout,
recovery, and retire (and delete a bunch of code), but the latter part
is on hold until drm/sched is fixed to properly handle job retire/
cleanup before deciding which job triggered the fault/timeout[1]. But
From: Rob Clark
The struct_mutex locking is a remnant from the days before per-obj locks,
and no longer needed.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_debugfs.c | 37 ++-
drivers/gpu/drm/msm/msm_fbdev.c | 13 ---
2 files changed, 16 insertion
From: Rob Clark
cur_ctx_seqno already does the same thing, but handles the edge cases
where a refcnt'd context can live after lastclose. So let's not have
two ways to do the same thing.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 3 +--
drivers/gpu/drm/msm/adreno/a3x
From: Rob Clark
The remaining struct_mutex usage is just to serialize various gpu
related things (submit/retire/recover/fault/etc), so replace
struct_mutex with gpu->lock.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 4 ++--
drivers/gpu/drm/msm/adreno/adreno_devic
From: Rob Clark
Add some helpers for fence comparision, which handle rollover properly,
and stop open coding fence seqno comparisions.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_fence.h | 12
drivers/gpu/drm/msm/msm_gpu.c | 6 +++---
drivers/gpu/drm/msm/msm_gpu.h |
From: Rob Clark
Add a debugfs interface to ignore hw error irqs, in order to force
fallback to sw hangcheck mechanism. Because the hw error detection is
pretty good on newer gens, we need this for igt tests to test the sw
hang detection.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
As we are going to add virtual planes, add the list of supported
formats
to the hw catalog entry. It will be used to setup universal planes,
with
later selecting a pipe depending on whether the YUV format is used for
the framebuffer.
Signed-off-by:
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
Add DPU_SSPP_CSC_ANY denoting any CSC block. As we are at it, rewrite
DPU_SSPP_SCALER (any scaler) to use BIT(x) instead of hand-coded
bitshifts.
This can go independent of the multi-rect series, so can you please take
this with the
first half of th
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
Stop limiting zpos property values, we use normalized_zpos anyway. And
nothing stops userspace from assigning several planes to a single zpos
(it is a userspace bug, but the kernel is forgiving about it).
Userspace assigning several planes to a singl
On Tue, 9 Nov 2021 at 23:15, wrote:
>
> On 2021-07-04 18:21, Dmitry Baryshkov wrote:
> > Stop limiting zpos property values, we use normalized_zpos anyway. And
> > nothing stops userspace from assigning several planes to a single zpos
> > (it is a userspace bug, but the kernel is forgiving about i
From: Kuogee Hsieh
Current DP drivers have regulators, clocks, irq and phy are grouped
together within a function and executed not in a symmetric manner.
This increase difficulty of code maintenance and limited code scalability.
This patch divided the driver life cycle of operation into four stat
Quoting Bjorn Andersson (2021-11-06 10:22:46)
> Since '8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon
> Chipsets")' the hpd_high member of struct dp_usbpd has been write-only.
>
> Let's clean up the code a little bit by removing the writes as well.
>
> Signed-off-by: Bjorn Anderss
Quoting Krishna Manikandan (2021-11-09 01:47:28)
> In the current implementation, substring comparison
> using device node name is used to find mdp node
> during driver probe. Use compatible string list instead
> of node name to get mdp node from the parent mdss node.
>
> Signed-off-by: Krishna Man
On 2021-11-09 10:04, Douglas Anderson wrote:
If you happened to try to access `/dev/drm_dp_aux` devices provided by
the MSM DP AUX driver too early at bootup you could go boom. Let's
avoid that by only allowing AUX transfers when the controller is
powered up.
Specifically the crash that was seen
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
Add support for handling and allocting SSPP blocks through the resource
manager. Handling code is not converted to use it though.
Signed-off-by: Dmitry Baryshkov
Conceptually this is identical to the previous attempt from QC on this:
https://patch
On 2021-11-09 12:21, Dmitry Baryshkov wrote:
On Tue, 9 Nov 2021 at 23:15, wrote:
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
> Stop limiting zpos property values, we use normalized_zpos anyway. And
> nothing stops userspace from assigning several planes to a single zpos
> (it is a userspace b
Hi Doug
On 11/9/2021 10:04 AM, Douglas Anderson wrote:
If you happened to try to access `/dev/drm_dp_aux` devices provided by
the MSM DP AUX driver too early at bootup you could go boom. Let's
avoid that by only allowing AUX transfers when the controller is
powered up.
Specifically the crash th
On Wed, 10 Nov 2021 at 04:35, wrote:
>
> On 2021-11-09 12:21, Dmitry Baryshkov wrote:
> > On Tue, 9 Nov 2021 at 23:15, wrote:
> >>
> >> On 2021-07-04 18:21, Dmitry Baryshkov wrote:
> >> > Stop limiting zpos property values, we use normalized_zpos anyway. And
> >> > nothing stops userspace from as
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
Downstream driver uses dpu->caps->smart_dma_rev to update
sspp->cap->features with the bit corresponding to the supported
SmartDMA
version. Upstream driver does not do this, resulting in SSPP subdriver
not enbaling setup_multirect callback. Make SSPP
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
Client driven prefetch (CDP) is properly setup only for SSPP REC0
currently. Enable client driven prefetch also for SSPP REC1.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 12 +++
On 2021-07-04 18:21, Dmitry Baryshkov wrote:
If SmartDMA is supported by the hardware, SSPPs allow using two RGB
layers per the hardware pipe (with some additional restrictions, like
no
support for scaling, etc). Register additional planes (two per the
SSPP)
and check if we can use multirect d
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