[Freedreno] [v1] drm/msm/dsi: save pll state before dsi host is powered off

Save pll state before dsi host is powered off. Without this change some register values gets resetted. Signed-off-by: Harigovindan P --- Changes in v1: - Saving pll state before dsi host is powered off. - Removed calling of save state in post_disable since everything woul

[Freedreno] [v1] drm/msm/dsi: save pll state before dsi host is powered off

Save pll state before dsi host is powered off. Without this change some register values gets resetted. Signed-off-by: Harigovindan P --- Changes in v1: - Saving pll state before dsi host is powered off. - Removed calling of save state in msm_dsi_phy_disable since everything

[Freedreno] [v1] drm/msm/dsi/pll: call vco set rate explicitly

For a given byte clock, if VCO recalc value is exactly same as vco set rate value, vco_set_rate does not get called assuming VCO is already set to required value. But Due to GDSC toggle, VCO values are erased in the HW. To make sure VCO is programmed correctly, we forcefully call set_rate from vco_

Re: [Freedreno] [v1] drm/msm/dsi: save pll state before dsi host is powered off

On Thu, Feb 6, 2020 at 1:52 AM Harigovindan P wrote: > > Save pll state before dsi host is powered off. Without this change > some register values gets resetted. The phy driver already does this. Why is the current implementation insufficient? > > Signed-off-by: Harigovindan P > --- > > Change

Re: [Freedreno] [v1] drm/msm/dsi/pll: call vco set rate explicitly

On Thu, Feb 6, 2020 at 2:13 AM Harigovindan P wrote: > > For a given byte clock, if VCO recalc value is exactly same as > vco set rate value, vco_set_rate does not get called assuming > VCO is already set to required value. But Due to GDSC toggle, > VCO values are erased in the HW. To make sure VC

Re: [Freedreno] [PATCH v3] drm/msm: Add syncobj support.

Hi, I'd appreciate if you could take a look at this patch. I believe I have accommodated the earlier review comments. Thank you, Bas On Fri, Jan 24, 2020 at 12:58 AM Bas Nieuwenhuizen wrote: > > This > > 1) Enables core DRM syncobj support. > 2) Adds options to the submission ioctl to wait/sign

Re: [Freedreno] [PATCH v2] drm/msm: Fix a6xx GMU shutdown sequence

Hi, On Wed, Feb 5, 2020 at 1:00 PM Rob Clark wrote: > > On Wed, Feb 5, 2020 at 12:48 PM Jordan Crouse wrote: > > > > Commit e812744c5f95 ("drm: msm: a6xx: Add support for A618") missed > > updating the VBIF flush in a6xx_gmu_shutdown and instead > > inserted the new sequence into a6xx_pm_suspend

Re: [Freedreno] [v1] dt-bindings: msm:disp: update dsi and dpu bindings

On Tue, Feb 04, 2020 at 07:45:37PM +0530, Harigovindan P wrote: > Updating bindings of dsi and dpu by adding and removing certain > properties. Yes, the diff tells me that. The commit message should say why. This change breaks compatibility as well. > > Signed-off-by: Harigovindan P > --- > >