Re: [PATCH v2 2/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver

On Wed, Feb 05, 2025 at 02:42:03PM +0100, Krzysztof Kozlowski wrote: > On 05/02/2025 12:23, Dmitry Baryshkov wrote: > + > +static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) > +{ > +dsi_pll_cmn_clk_cfg1_update(pll, BIT(5), 0); > } >

Re: [PATCH v2 2/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver

On 05/02/2025 12:23, Dmitry Baryshkov wrote: + +static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) +{ +dsi_pll_cmn_clk_cfg1_update(pll, BIT(5), 0); } static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)

Re: [PATCH v2 2/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver

Hi, On Wed, 5 Feb 2025 at 11:34, Krzysztof Kozlowski wrote: > > On 05/02/2025 03:51, Dmitry Baryshkov wrote: > > On Tue, Feb 04, 2025 at 04:46:04PM +0100, Krzysztof Kozlowski wrote: > >> On 04/02/2025 15:26, Dmitry Baryshkov wrote: > >>> On Tue, Feb 04, 2025 at 10:21:25AM +0100, Krzysztof Kozlows

Re: [PATCH v2 2/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver

On 05/02/2025 03:51, Dmitry Baryshkov wrote: > On Tue, Feb 04, 2025 at 04:46:04PM +0100, Krzysztof Kozlowski wrote: >> On 04/02/2025 15:26, Dmitry Baryshkov wrote: >>> On Tue, Feb 04, 2025 at 10:21:25AM +0100, Krzysztof Kozlowski wrote: On 03/02/2025 18:41, Dmitry Baryshkov wrote: > On Mon

Re: [PATCH v2 2/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver

On Tue, Feb 04, 2025 at 04:46:04PM +0100, Krzysztof Kozlowski wrote: > On 04/02/2025 15:26, Dmitry Baryshkov wrote: > > On Tue, Feb 04, 2025 at 10:21:25AM +0100, Krzysztof Kozlowski wrote: > >> On 03/02/2025 18:41, Dmitry Baryshkov wrote: > >>> On Mon, Feb 03, 2025 at 06:29:19PM +0100, Krzysztof Ko

Re: [PATCH v2 2/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver

On 04/02/2025 15:26, Dmitry Baryshkov wrote: > On Tue, Feb 04, 2025 at 10:21:25AM +0100, Krzysztof Kozlowski wrote: >> On 03/02/2025 18:41, Dmitry Baryshkov wrote: >>> On Mon, Feb 03, 2025 at 06:29:19PM +0100, Krzysztof Kozlowski wrote: PHY_CMN_CLK_CFG1 register is updated by the PHY driver an

Re: [PATCH v2 2/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver

On Tue, Feb 04, 2025 at 10:21:25AM +0100, Krzysztof Kozlowski wrote: > On 03/02/2025 18:41, Dmitry Baryshkov wrote: > > On Mon, Feb 03, 2025 at 06:29:19PM +0100, Krzysztof Kozlowski wrote: > >> PHY_CMN_CLK_CFG1 register is updated by the PHY driver and by a mux > >> clock from Common Clock Framewor

Re: [PATCH v2 2/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver

On 03/02/2025 18:41, Dmitry Baryshkov wrote: > On Mon, Feb 03, 2025 at 06:29:19PM +0100, Krzysztof Kozlowski wrote: >> PHY_CMN_CLK_CFG1 register is updated by the PHY driver and by a mux >> clock from Common Clock Framework: >> devm_clk_hw_register_mux_parent_hws(). There could be a path leading t

Re: [PATCH v2 2/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver

On Mon, Feb 03, 2025 at 06:29:19PM +0100, Krzysztof Kozlowski wrote: > PHY_CMN_CLK_CFG1 register is updated by the PHY driver and by a mux > clock from Common Clock Framework: > devm_clk_hw_register_mux_parent_hws(). There could be a path leading to > concurrent and conflicting updates between PHY

[PATCH v2 2/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver

PHY_CMN_CLK_CFG1 register is updated by the PHY driver and by a mux clock from Common Clock Framework: devm_clk_hw_register_mux_parent_hws(). There could be a path leading to concurrent and conflicting updates between PHY driver and clock framework, e.g. changing the mux and enabling PLL clocks.