On 08/10/2024 14:25, Jessica Zhang wrote:
On 10/8/2024 1:00 AM, Neil Armstrong wrote:
Hi,
On 01/10/2024 09:37, neil.armstr...@linaro.org wrote:
Hi,
On 30/09/2024 21:19, Jessica Zhang wrote:
On 9/30/2024 7:17 AM, neil.armstr...@linaro.org wrote:
On 25/09/2024 00:59, Jessica Zhang wrote:
On 10/8/2024 1:00 AM, Neil Armstrong wrote:
Hi,
On 01/10/2024 09:37, neil.armstr...@linaro.org wrote:
Hi,
On 30/09/2024 21:19, Jessica Zhang wrote:
On 9/30/2024 7:17 AM, neil.armstr...@linaro.org wrote:
On 25/09/2024 00:59, Jessica Zhang wrote:
When running igt-test on QRD8650, I
On Tue, Oct 08, 2024 at 10:00:57AM GMT, Neil Armstrong wrote:
> Hi,
>
> On 01/10/2024 09:37, neil.armstr...@linaro.org wrote:
> > Hi,
> >
> > On 30/09/2024 21:19, Jessica Zhang wrote:
> > >
> > >
> > > On 9/30/2024 7:17 AM, neil.armstr...@linaro.org wrote:
> > > > On 25/09/2024 00:59, Jessica Z
Hi,
On 01/10/2024 09:37, neil.armstr...@linaro.org wrote:
Hi,
On 30/09/2024 21:19, Jessica Zhang wrote:
On 9/30/2024 7:17 AM, neil.armstr...@linaro.org wrote:
On 25/09/2024 00:59, Jessica Zhang wrote:
When running igt-test on QRD8650, I get:
# IGT_FRAME_DUMP_PATH=$PWD FRAME_PNG_FILE_N
Hi,
On 30/09/2024 21:19, Jessica Zhang wrote:
On 9/30/2024 7:17 AM, neil.armstr...@linaro.org wrote:
On 25/09/2024 00:59, Jessica Zhang wrote:
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-b
On 9/30/2024 7:17 AM, neil.armstr...@linaro.org wrote:
On 25/09/2024 00:59, Jessica Zhang wrote:
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dis
On 25/09/2024 00:59, Jessica Zhang wrote:
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 83 +-
d
On Tue, Sep 24, 2024 at 05:14:49PM GMT, Jessica Zhang wrote:
>
>
> On 9/24/2024 4:41 PM, Dmitry Baryshkov wrote:
> > On Tue, Sep 24, 2024 at 03:59:32PM GMT, Jessica Zhang wrote:
> > > Cache the CWB block mask in the DPU virtual encoder and configure CWB
> > > according to the CWB block mask withi
On 9/24/2024 4:41 PM, Dmitry Baryshkov wrote:
On Tue, Sep 24, 2024 at 03:59:32PM GMT, Jessica Zhang wrote:
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-by: Jessica Zhang
---
drivers/gpu/d
On Tue, Sep 24, 2024 at 03:59:32PM GMT, Jessica Zhang wrote:
> Cache the CWB block mask in the DPU virtual encoder and configure CWB
> according to the CWB block mask within the writeback phys encoder
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 8
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 83 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.
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