Re: [Freedreno] [v1 2/3] drm/msm/dsi: Add PHY configuration for SC7280

2021-06-01 Thread rajeevny
On 31-05-2021 23:27, Dmitry Baryshkov wrote: On 31/05/2021 16:33, Rajeev Nandan wrote: + .min_pll_rate = 6UL, + .max_pll_rate = (50ULL < ULONG_MAX) ? 50ULL : ULONG_MAX, Could you please follow the patch by Arnd here? https://lore.kernel.org/linux-arm-msm/20210

Re: [Freedreno] [v1 2/3] drm/msm/dsi: Add PHY configuration for SC7280

2021-05-31 Thread Dmitry Baryshkov
On 31/05/2021 16:33, Rajeev Nandan wrote: The SC7280 SoC uses the 7nm (V4.1) DSI PHY driver with different enable|disable regulator loads. Signed-off-by: Rajeev Nandan --- drivers/gpu/drm/msm/Kconfig | 6 +++--- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/d

[Freedreno] [v1 2/3] drm/msm/dsi: Add PHY configuration for SC7280

2021-05-31 Thread Rajeev Nandan
The SC7280 SoC uses the 7nm (V4.1) DSI PHY driver with different enable|disable regulator loads. Signed-off-by: Rajeev Nandan --- drivers/gpu/drm/msm/Kconfig | 6 +++--- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gp