On Thu, Nov 30, 2023 at 1:21 PM Rob Clark wrote:
>
> From: Rob Clark
>
> The UBWC settings need to match between the display and GPU. When we
> updated the GPU settings, we forgot to make the corresponding update on
> the display side.
>
> Reported-by: Steev Klimaszewsk
= {0xf, 0x, 0x0},
> + .safe_lut_tbl = {0xfe00, 0xfe00, 0x},
> .qos_lut_tbl = {
> {.nentry = ARRAY_SIZE(sc8180x_qos_linear),
> .entries = sc8180x_qos_linear
>
> ---
> base-commit: c503e3eec382ac708ee7adf874add37b77c5d312
> change-id: 20231030-sc8280xp-dpu-safe-lut-9769027b8452
>
> Best regards,
> --
> Bjorn Andersson
>
Tested-by: Steev Klimaszewski
> --
> 2.39.2
>
Tested here on my X13s with GNOME 44.1 and using Wayland.
Tested-by: Steev Klimaszewski
Hi Dmitry
On Sun, May 21, 2023 at 12:28 PM Dmitry Baryshkov
wrote:
>
> Both DPU and MDSS programming requires knowledge of some of UBWC
> parameters. This results in duplication of UBWC data between MDSS and
> DPU drivers. To remove such duplication and make the driver more
> error-prone, export
---[ end trace ]---
Signed-off-by: Steev Klimaszewski
---
drivers/gpu/drm/msm/msm_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 8b0b0ac74a6f..65c4c93c311e 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
++
p-dpu.yaml
> create mode 100644
> Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml
>
> --
> 2.37.3
>
Tested on Lenovo Thinkpad X13s
Tested-by: Steev Klimaszewski
reg = <0 0x0ae96400 0 0x200>,
<0 0x0ae96600 0 0x280>,
Tested on Lenovo Yoga C630
Tested-by: Steev Klimaszewski
Hi Johan,
On Wed, Sep 14, 2022 at 1:01 AM Johan Hovold wrote:
>
> On Tue, Sep 13, 2022 at 03:23:10PM -0500, Steev Klimaszewski wrote:
> > Hi Johan,
> >
> > On 9/13/22 3:53 AM, Johan Hovold wrote:
> > > The MSM DRM driver is currently broken in multiple ways wit
Hi Johan,
On 9/13/22 3:53 AM, Johan Hovold wrote:
The MSM DRM driver is currently broken in multiple ways with respect to
probe deferral. Not only does the driver currently fail to probe again
after a late deferral, but due to a related use-after-free bug this also
triggers NULL-pointer derefere
On 9/12/22 1:10 PM, Dmitry Baryshkov wrote:
On 12/09/2022 18:40, Johan Hovold wrote:
Device-managed resources allocated post component bind must be tied to
the lifetime of the aggregate DRM device or they will not necessarily be
released when binding of the aggregate device is deferred.
This
On Wed, Aug 10, 2022 at 11:28 PM Steev Klimaszewski wrote:
>
> Hi Bjorn,
>
>
> On Wed, Aug 10, 2022 at 10:58 PM Bjorn Andersson
> wrote:
> >
> > The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9
> > interfaces, 2 DSI controllers and 4
Hi Bjorn,
On Wed, Aug 10, 2022 at 10:58 PM Bjorn Andersson
wrote:
>
> The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9
> interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the
> necessary definitions and describe the DPU in the SC8280XP.
>
> Signed-off-by: Bjorn
ted_aux;
+ if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
+ return 0;
+
pdata->connector = drm_bridge_connector_init(pdata->bridge.dev,
pdata->bridge.encoder);
if (IS_ERR(pdata->connector)) {
Tested on Lenovo Yoga C630
Tested-by: Steev Klimaszewski
min_dp_rate_idx(pdata, bpp);
dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
dp_rate_idx++) {
if (!(valid_rates & BIT(dp_rate_idx)))
Tested on the Lenovo Yoga C630. bpc is found to be 6, which I believe
is correct.
Tested-by: Steev Klimaszewski
again with
the correct value. But we should just not do this. Instead
just leave a sanity check that the fence looks plausible (in
case the GPU scribbled on memory).
Reported-by: Steev Klimaszewski
Fixes: 95d1deb02a9c ("drm/msm/gem: Add fenced vma unpin")
Signed-off-by: Rob Clark
---
d
. But walking the list of submits in the
irq handler isn't really needed, as dma_fence_is_signaled() will dtrt.
So lets just drop it entirely.
Reported-by: Steev Klimaszewski
Fixes: 95d1deb02a9c ("drm/msm/gem: Add fenced vma unpin")
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm
aspace->lock);
if (vma->iova)
I've seen the splat on the Lenovo Yoga C630 here, and have tested this
patch, and as described, the splat still happens, but the system is
still able to be used.
Tested-by: Steev Klimaszewski
ge from v1 :D
Tested-By: Steev Klimaszewski
On 11/4/21 5:28 PM, Rob Clark wrote:
From: Rob Clark
Reported-by: Douglas Anderson
Fixes: 9bc95570175a ("drm/msm: Devfreq tuning")
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/ms
On 10/14/21 10:42 AM, Steev Klimaszewski wrote:
On 10/14/21 8:54 AM, Dmitry Baryshkov wrote:
From: Amit Pundir
This reverts commit 001ce9785c0674d913531345e86222c965fc8bf4.
This upstream commit broke AOSP (post Android 12 merge) build
on RB5. The device either silently crashes into USB
On 10/14/21 8:54 AM, Dmitry Baryshkov wrote:
From: Amit Pundir
This reverts commit 001ce9785c0674d913531345e86222c965fc8bf4.
This upstream commit broke AOSP (post Android 12 merge) build
on RB5. The device either silently crashes into USB crash mode
after android boot animation or we see a b
gt;Code: aa0003f5 a90153f3 f8408eb3 aa1303e0 (f85e8674)
>---[ end trace 39b2fa37509a2be2 ]---
> Fixing recursive fault but reboot is needed!
>
> Fixes: 86c2a0f000c1 drm/msm: ("Small submitqueue creation cleanup")
> Reported-by: Steev Klimaszewski
> Signed-off-b
On 3/31/21 7:34 AM, kalya...@codeaurora.org wrote:
> On 2021-03-31 00:04, Steev Klimaszewski wrote:
>> On 3/22/21 4:17 AM, Kalyan Thota wrote:
>>> From: Kalyan Thota
>>>
>>> DPU runtime resume will request for a min vote on the AXI bus as
>>> it
On 3/22/21 4:17 AM, Kalyan Thota wrote:
> From: Kalyan Thota
>
> DPU runtime resume will request for a min vote on the AXI bus as
> it is a necessary step before turning ON the AXI clock.
>
> The change does below
> 1) Move the icc path set before requesting runtime get_sync.
> 2) remove the dep
8 +231,7 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
> c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
> c->ops.get_line_count = dpu_hw_pp_get_line_count;
>
> - if (test_bit(DPU_PINGPONG_DITHER, &
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