To prevent incorrect BW calculation, zero out dpu_core_perf_params
before it is passed into dpu_core_perf_aggregate().
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1
Similar to WB_MUX, CDM_MUX also needs to be adjusted to support
dedicated CWB PINGPONGs
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
b/drivers/gpu
Now that CDM_0 has been enabled for DPU 5.x+, add support for YUV formats
on writeback
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog
extend the stage to an array with array
size STAGES_PER_PLANE and blend pipes per mixer pair with configuration
in the stage structure.
Signed-off-by: Jun Nie
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 46
denote number of pipes that
can be used by the plane.
Hi Jun,
Sorry for missing this in the last revision, but it seems to me that the
looping of the pipes in `_dpu_debugfs_status_show()` should also be
using PIPES_PER_PLANE.
Thanks,
Jessica Zhang
Signed-off-by: Jun Nie
Reviewed-by: Dmitry
On 3/3/2025 3:49 PM, Dmitry Baryshkov wrote:
On Mon, Mar 03, 2025 at 10:28:00AM -0800, Jessica Zhang wrote:
If new CTLs are reserved by CRTC but atomic_enable() is skipped, the
encoders will configure the stale CTL instead of the newly reserved one.
The CTLs are propagates in
On 2/27/2025 7:07 AM, Dmitry Baryshkov wrote:
On Fri, Feb 14, 2025 at 04:14:26PM -0800, Jessica Zhang wrote:
From: Dmitry Baryshkov
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to use CRTC id in preparation for the next step.
Reviewed-by: Abhinav
eventually
all HW blocks used by encoders (i.e. DSC, PINGPONG, CWB) should have a
similar check to avoid the same issue.
Suggested-by: Abhinav Kumar
Closes:
https://lists.freedesktop.org/archives/freedreno/2025-February/036719.html
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1
On 2/26/2025 6:28 PM, Jun Nie wrote:
Jessica Zhang 于2025年2月27日周四 02:10写道：
On 2/26/2025 4:31 AM, Jun Nie wrote:
Currently, SSPPs are assigned to a maximum of two pipes. However,
quad-pipe usage scenarios require four pipes and involve configuring
two stages. In quad-pipe case, the first
for (i = 0; i < PIPES_PER_STAGE; i++)
+ for (i = 0; i < PIPES_PER_PLANE; i++)
Hi Jun,
Is there a reason why only this case was changed to PIPES_PER_PLANE but
_dpu_plane_color_fill() only loops over PIPES_PER_STAGE?
Similarly, I see that dpu_plane_danger_sign
Nie
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 35 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 169 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 12 +--
3 files changed, 113 insertions
actor
2. This mode_changed() series
3. The rest of the CWB series
This will cause some merge conflicts with the CRTC RM refactor though
and you'll need to move the dpu_kms changes in [1] to this patch.
What do you think?
Thanks,
Jessica Zhang
[1] https://patchwork.freedesktop.org/patch/637487/
r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+ num_lm = dpu_crtc_get_num_lm(crtc_state);
Hi Jun,
Just wondering, why not use dpu_rm_get_assigned_resources() here instead
of adding a new *_get_num_lm() API?
Thanks,
Jessica Zhang
+ num_stages = (num_lm + 1
On 2/17/2025 8:41 AM, Krzysztof Kozlowski wrote:
The set_active_pipes() callback configures CTL_FETCH_PIPE_ACTIVE and
newer DPU v12.0 comes with CTL_PIPE_ACTIVE, thus rename it to
set_active_fetch_pipes() to better match the purpose.
Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Jessica
Hi Krzysztof,
I see that this line was only previously removed in a patch that was in
an older revision of your PHY_CMN_CLK_CFG[01] improvements series
("drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1 when choosing bitclk
source").
Did you mean for this patch/series
On 2/17/2025 8:41 AM, Krzysztof Kozlowski wrote:
MDSS/MDP v12 comes with new bits in flush registers (e.g.
MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7.
Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++
1 file
On 2/17/2025 8:41 AM, Krzysztof Kozlowski wrote:
Drop comments about SoC before each 'struct dpu_lm_sub_blks' for given
SoC because it's duplicating the actual name of structure.
Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Jessica Zhang
---
drivers/gpu/dr
On 2/17/2025 8:41 AM, Krzysztof Kozlowski wrote:
Add IDs for new blocks present in MDSS/MDP v12 for LM, DSC, PINGPONG and
MERGE_3D blocks.
Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 6 ++
1 file changed, 6
On 2/17/2025 8:41 AM, Krzysztof Kozlowski wrote:
Add IDs for new blocks present in MDSS/MDP v12 for LM, DSC, PINGPONG and
MERGE_3D blocks.
Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 6 ++
1 file changed, 6
f this series until the DSI
panel comes up for MTP8750?
Thanks,
Jessica Zhang
Best regards,
Krzysztof
---
Krzysztof Kozlowski (16):
dt-bindings: display/msm: dsi-controller-main: Combine if:then: entries
dt-bindings: display/msm: dsi-controller-main: Add missing minItems
From: Abhinav Kumar
Introduce a new API msm_iommu_disp_new() for display use-cases.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_iommu.c | 26 ++
drivers/gpu/drm/msm/msm_mmu.h | 1 +
2 files
From: Abhinav Kumar
Switch msm_kms to use msm_iommu_disp_new() so that the newly
registered fault handler will kick-in during any mmu faults.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_kms.c | 2 +-
1 file changed, 1
debug display mmu faults.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_kms.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c
index
/gpu/drm/msm/msm_mmu.h| 1 +
5 files changed, 52 insertions(+), 4 deletions(-)
---
base-commit: 866e43b945bf98f8e807dfa45eca92f931f3a032
change-id: 20241217-abhinavk-smmu-fault-handler-ade75fef9809
Best regards,
--
Jessica Zhang
From: Abhinav Kumar
In preparation of registering a separate fault handler for
display, lets rename the existing msm_fault_handler to
msm_gpu_fault_handler.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_iommu.c | 6
capture
the snapshot for debugging otherwise there will be a lot of DPU
snapshots getting captured for the same fault which is redundant
and also might affect capturing even one snapshot accurately.
Signed-off-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
Changes in v3:
- Clear
lm_count
to an even number instead of completely clearing it. This prevents all
pairs from being cleared in cases where multiple LM pairs are needed.
Signed-off-by: Jun Nie
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 6 +-
1 file changed, 5 insertions(+), 1
Baryshkov
Signed-off-by: Jessica Zhang
---
Changes in v6:
- Do not return early if encoder_mask is 0
Changes in v5:
- Reordered to prevent breaking CI or upon partial application
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 63 +
drivers/gpu/drm/msm/disp/dpu1
kickoff is finished
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 4 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 27 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 3
On 1/17/2025 8:00 AM, Jun Nie wrote:
Add pipe as trace argument in trace_dpu_crtc_setup_mixer() to ease
converting pipe into pipe array later.
Signed-off-by: Jun Nie
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2
From: Dmitry Baryshkov
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to use CRTC id in preparation for the next step.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
Changes in
Nie
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 7191b1a6d41b3
easily understand
which resource caused the failure, so add a table to match the type ID
to an human readable resource name and use it in the error print.
Signed-off-by: Jun Nie
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 23 +++
1 file changed
If the clone mode enabled status is changing, a modeset needs to happen
so that the resources can be reassigned
Reviewed-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 17 -
drivers/gpu/drm/msm/disp
: Refactored resource allocation for CDM]
Signed-off-by: Abhinav Kumar
[quic_jessz...@quicinc.com: Changed to grabbing exising global state]
Signed-off-by: Jessica Zhang
---
Changes in v6:
- Added note on duplicated checks in dpu_encoder_needs_modeset() and
dpu_encoder_update_topology() (Dmitry)
Changes
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 75
how many
outputs are requesting CDM block. Return EINVAL if multiple outputs are
trying to reserve CDM.
Signed-off-by: Jessica Zhang
---
Changes in v6:
- cdm_requested -> num_cdm
Changes in v5:
- Changed check to fail only if multiple outputs are requesting CDM
simultaneously
---
drivers/
The CWB mux has a pending flush bit and *_active register.
Add support for configuring them within the dpu_hw_ctl layer.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 13 ++
.../gpu/drm
kicked off to ensure that we don't get timeouts when the
system has a heavy load (ex. when debug logs are enabled)
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 74 ++--
1
encoders
only if CWB is not enabled.
Reviewed-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
Changes in v5:
- Reworded commit message to be more specific
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
For concurrent writeback, the real time encoder is responsible for
trigger flush and trigger start. Return early for trigger start and
trigger flush for the concurrent writeback encoders.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm
Set writeback encoders as possible clones for DSI encoders and vice
versa.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 32 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2
state and add a CWB-specific helper to
reserve the correct CWB muxes and dedicated PINGPONGs following the
even/odd rule.
Signed-off-by: Jessica Zhang
---
Changes in v6:
- Add a comment on using the RM HW block array index to enforce the CWB
odd/even rule (Dmitry)
Changes in v5:
- Allocate CWB
Adjust QoS remapper, OT limit, and CDP parameters to account for
concurrent writeback
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions
source allocation to CRTC
drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation
Jessica Zhang (11):
drm/msm/dpu: Add CWB to msm_display_topology
drm/msm/dpu: Require modeset if clone mode status changes
drm/msm/dpu: Fail atomic_check if multiple outputs requ
/jr7zbj5w7iq4apg3gofuvcwf4r2swzqjk7sshwcdjll4mn6ctt@l2n3qfpujg3q/
Signed-off-by: Jessica Zhang
---
This was tested on SC7180 Trogdor by pulling in the concurrent writeback
series [1] and running the IGT kms_writeback@writeback_check_output
subtest.
[1] https://patchwork.freedesktop.org/series/144083
available in dsc->slice_count which is per-interface by the current
design of MSM DPU/DSI implementations and their use of the DRM DSC
helpers.
Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
Signed-off-by: Marijn Suijten
Hi Marijn,
Reviewed-by: Jessica Z
er.
Fixes: 7e9cc175b159 ("drm/msm/disp/dpu1: Add support for DSC in topology")
Signed-off-by: Marijn Suijten
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dis
: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index c734d2c5790d2..5b98ae96bf5d4
Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index eaac172141ede..c734d2c5790d2 100644
On 1/29/2025 2:04 PM, Dmitry Baryshkov wrote:
On Tue, Jan 28, 2025 at 07:20:34PM -0800, Jessica Zhang wrote:
From: Dmitry Baryshkov
All resource allocation is centered around the LMs. Then other blocks
(except DSCs) are allocated basing on the LMs that was selected, and LM
powers up the
On 1/29/2025 9:51 AM, Dmitry Baryshkov wrote:
On Tue, Jan 28, 2025 at 07:20:32PM -0800, Jessica Zhang wrote:
DPU supports a single writeback session running concurrently with primary
display when the CWB mux is configured properly. This series enables
clone mode for DPU driver and adds
On 1/29/2025 2:11 PM, Dmitry Baryshkov wrote:
On Tue, Jan 28, 2025 at 07:20:39PM -0800, Jessica Zhang wrote:
Add support for RM to reserve dedicated CWB PINGPONGs and CWB muxes
For concurrent writeback, even-indexed CWB muxes must be assigned to
even-indexed LMs and odd-indexed CWB muxes
For concurrent writeback, the real time encoder is responsible for
trigger flush and trigger start. Return early for trigger start and
trigger flush for the concurrent writeback encoders.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm
state and add a CWB-specific helper to
reserve the correct CWB muxes and dedicated PINGPONGs following the
even/odd rule.
Signed-off-by: Jessica Zhang
---
Changes in v5:
- Allocate CWB muxes first then allocate PINGPONG block based on CWB mux
index
- Corrected comment doc on odd/even rule
: Refactored resource allocation for CDM]
Signed-off-by: Abhinav Kumar
[quic_jessz...@quicinc.com: Changed to grabbing exising global state]
Signed-off-by: Jessica Zhang
---
Changes in v5:
- Reordered to prevent breaking CI and upon partial applciation
- Moved mode_changed() from dpu_encoder to dpu_crtc
The CWB mux has a pending flush bit and *_active register.
Add support for configuring them within the dpu_hw_ctl layer.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 13 ++
.../gpu/drm
m/dpu: fill CRTC resources in dpu_crtc.c
drm/msm/dpu: move resource allocation to CRTC
drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation
Jessica Zhang (11):
drm/msm/dpu: Add CWB to msm_display_topology
drm/msm/dpu: Require modeset if clone mode status
Set writeback encoders as possible clones for DSI encoders and vice
versa.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 32 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2
Baryshkov
Signed-off-by: Jessica Zhang
---
Changes in v5:
- Reordered to prevent breaking CI or upon partial application
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 66 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 37
2 files changed, 66 insertions
track how
many outputs are requesting CDM block. Return EINVAL if multiple outputs
are trying to reserve CDM.
Signed-off-by: Jessica Zhang
---
Changes in v5:
- Changed check to fail only if multiple outputs are requesting CDM
simultaneously
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4
From: Dmitry Baryshkov
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to use CRTC id in preparation for the next step.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
Changes in
encoders
only if CWB is not enabled.
Reviewed-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
Changes in v5:
- Reworded commit message to be more specific
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
Adjust QoS remapper, OT limit, and CDP parameters to account for
concurrent writeback
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions
kickoff is finished
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 4 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 27 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 3
If the clone mode enabled status is changing, a modeset needs to happen
so that the resources can be reassigned
Reviewed-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 17 -
drivers/gpu/drm/msm/disp
kicked off to ensure that we don't get timeouts when the
system has a heavy load (ex. when debug logs are enabled)
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 74 ++--
1
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 75
n Suijten
Hi Marijn,
Thanks for the patch. LGTM
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
---
Note that this doesn't paint the full picture in case there are SoCs
with more DSC hardware blocks, but when multiple virtual encoders
have already allocated most of them. My init
patchsets/revisions.
Thanks,
Jessica Zhang
The first pipe pair co-work with the first mixer pair to cover the left
half of screen and 2nd pair of pipes and mixers are for the right half
of screen. If a plane is only for the right half of screen, only one
or two of pipes in the 2nd pipe pair are
On 1/15/2025 1:56 AM, Dmitry Baryshkov wrote:
On Tue, Jan 14, 2025 at 09:28:50PM -0800, Jessica Zhang wrote:
On 12/24/2024 12:00 PM, Dmitry Baryshkov wrote:
On Tue, Dec 24, 2024 at 06:45:07AM +0200, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 at 04:43:17PM -0800, Jessica Zhang wrote
On 12/24/2024 12:00 PM, Dmitry Baryshkov wrote:
On Tue, Dec 24, 2024 at 06:45:07AM +0200, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 at 04:43:17PM -0800, Jessica Zhang wrote:
From: Dmitry Baryshkov
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to
On 1/9/2025 6:10 PM, Dmitry Baryshkov wrote:
On Thu, Jan 09, 2025 at 05:50:16PM -0800, Jessica Zhang wrote:
On 1/9/2025 5:42 PM, Dmitry Baryshkov wrote:
On Fri, 10 Jan 2025 at 02:30, Jessica Zhang wrote:
On 1/9/2025 4:00 PM, Dmitry Baryshkov wrote:
On Thu, Jan 09, 2025 at 02:34:44PM
On 1/9/2025 5:42 PM, Dmitry Baryshkov wrote:
On Fri, 10 Jan 2025 at 02:30, Jessica Zhang wrote:
On 1/9/2025 4:00 PM, Dmitry Baryshkov wrote:
On Thu, Jan 09, 2025 at 02:34:44PM -0800, Jessica Zhang wrote:
On 1/3/2025 10:16 AM, Dmitry Baryshkov wrote:
On Fri, Jan 03, 2025 at 10:03
On 1/9/2025 4:00 PM, Dmitry Baryshkov wrote:
On Thu, Jan 09, 2025 at 02:34:44PM -0800, Jessica Zhang wrote:
On 1/3/2025 10:16 AM, Dmitry Baryshkov wrote:
On Fri, Jan 03, 2025 at 10:03:35AM -0800, Jessica Zhang wrote:
On 12/19/2024 9:03 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024
On 1/9/2025 2:13 PM, Dmitry Baryshkov wrote:
On Thu, 9 Jan 2025 at 23:26, Jessica Zhang wrote:
On 12/28/2024 8:47 PM, Dmitry Baryshkov wrote:
On Thu, Dec 26, 2024 at 02:49:28PM -0800, Jessica Zhang wrote:
On 12/20/2024 5:07 PM, Dmitry Baryshkov wrote:
On Fri, Dec 20, 2024 at 04:12
On 1/3/2025 10:16 AM, Dmitry Baryshkov wrote:
On Fri, Jan 03, 2025 at 10:03:35AM -0800, Jessica Zhang wrote:
On 12/19/2024 9:03 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 at 04:43:26PM -0800, Jessica Zhang wrote:
Add the cwb_enabled flag to msm_display topology and adjust the
On 12/28/2024 8:47 PM, Dmitry Baryshkov wrote:
On Thu, Dec 26, 2024 at 02:49:28PM -0800, Jessica Zhang wrote:
On 12/20/2024 5:07 PM, Dmitry Baryshkov wrote:
On Fri, Dec 20, 2024 at 04:12:29PM -0800, Jessica Zhang wrote:
On 12/19/2024 9:52 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16
On 12/18/2024 11:49 PM, Jun Nie wrote:
There are 2 interfaces and 4 pingpong in quad pipe. Map the 2nd
interface to 3rd PP instead of the 2nd PP.
Signed-off-by: Jun Nie
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 15
"Reset lm_count to an even
index. This will drop the previous primary mixer if ..."
+*/
+ lm_count &= 0xfe;
Nit: Can we directly clear the first bit instead of doing an 8-bit bitmask?
Thanks,
Jessica Zhang
message on why the last bit check
works?
Thanks,
Jessica Zhang
Signed-off-by: Jun Nie
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers
disable the cursor
plane to be blocking commits. This will ensure that hardware clears and
stops fetching the FB source address before the driver deallocates the FB
Fixes: 2d99ced787e3 ("drm/msm: async commit support")
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_ato
Initialize the return value so that the dpu_crtc_atomic_check() doesn't
fail if the virtual planes command line parameter is enabled and no planes
are visible.
Fixes: 774bcfb73176 ("drm/msm/dpu: add support for virtual planes")
Signed-off-by: Jessica Zhang
---
drivers/gpu/dr
Drop extra return at the end of dpu_crtc_reassign_planes()
Fixes: 774bcfb73176 ("drm/msm/dpu: add support for virtual planes")
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/
e for dpu_crtc_reassign_planes()
These were discovered when setting `msm.dpu_use_virtual_planes=1` in the
command line arguments, but not forcing virtual planes to be used.
Signed-off-by: Jessica Zhang
---
Jessica Zhang (2):
drm/msm/dpu: Initialize return value for dpu_assign_plane_resources()
On 12/19/2024 9:03 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 at 04:43:26PM -0800, Jessica Zhang wrote:
Add the cwb_enabled flag to msm_display topology and adjust the toplogy
to account for concurrent writeback
Why?
Hi Dmitry,
This flag is necessary to specify that CWB mux(es
On 12/19/2024 9:44 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 at 04:43:28PM -0800, Jessica Zhang wrote:
We cannot support both CWB and CDM simultaneously as this would require
2 CDM blocks and currently our hardware only supports 1 CDM block at
most.
Why would CWB require a second
On 12/20/2024 5:07 PM, Dmitry Baryshkov wrote:
On Fri, Dec 20, 2024 at 04:12:29PM -0800, Jessica Zhang wrote:
On 12/19/2024 9:52 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 at 04:43:29PM -0800, Jessica Zhang wrote:
Add support for RM to reserve dedicated CWB PINGPONGs and CWB muxes
On 12/19/2024 9:52 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 at 04:43:29PM -0800, Jessica Zhang wrote:
Add support for RM to reserve dedicated CWB PINGPONGs and CWB muxes
For concurrent writeback, even-indexed CWB muxes must be assigned to
even-indexed LMs and odd-indexed CWB muxes
On 12/19/2024 9:11 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 at 04:43:11PM -0800, Jessica Zhang wrote:
DPU supports a single writeback session running concurrently with primary
display when the CWB mux is configured properly. This series enables
clone mode for DPU driver and adds
On 12/18/2024 3:20 AM, Dmitry Baryshkov wrote:
On Tue, Dec 17, 2024 at 04:27:57PM -0800, Jessica Zhang wrote:
From: Abhinav Kumar
There is no recovery mechanism in place yet to recover from mmu
faults for DPU. We can only prevent the faults by making sure there
is no misconfiguration
From: Abhinav Kumar
In preparation of registering a separate fault handler for
display, lets rename the existing msm_fault_handler to
msm_gpu_fault_handler.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_iommu.c | 6
| 3 +++
drivers/gpu/drm/msm/msm_mmu.h| 1 +
5 files changed, 52 insertions(+), 4 deletions(-)
---
base-commit: 86313a9cd152330c634b25d826a281c6a002eb77
change-id: 20241217-abhinavk-smmu-fault-handler-ade75fef9809
Best regards,
--
Jessica Zhang
From: Abhinav Kumar
Switch msm_kms to use msm_iommu_disp_new() so that the newly
registered fault handler will kick-in during any mmu faults.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_kms.c | 2 +-
1 file changed, 1
From: Abhinav Kumar
Introduce a new API msm_iommu_disp_new() for display use-cases.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_iommu.c | 26 ++
drivers/gpu/drm/msm/msm_mmu.h | 1 +
2 files
capture
the snapshot for debugging otherwise there will be a lot of DPU
snapshots getting captured for the same fault which is redundant
and also might affect capturing even one snapshot accurately.
Signed-off-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_atomic.c | 2
debug display mmu faults.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_kms.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c
index
The CWB mux has a pending flush bit and *_active register.
Add support for configuring them within the dpu_hw_ctl layer.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 13 ++
.../gpu/drm/msm/disp/dpu1
Set writeback encoders as possible clones for DSI encoders and vice
versa.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 32 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 ++
drivers/gpu/drm/msm
From: Dmitry Baryshkov
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to use CRTC id in preparation for the next step.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
Changes in v4 (due to rebase):
- moved
1 - 100 of 747 matches
Mail list logo
