s in the display data path.
> 3) Attach the reserved block to the encoder.
>
> Signed-off-by: Kalyan Thota
Tested-by: Fritz Koenig
> ---
> drivers/gpu/drm/msm/Makefile | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 +
> drivers/gpu/drm/msm/disp/
NV12 is a valid format for UBWC
Signed-off-by: Fritz Koenig
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h
index
Hardware only natively supports BGR UBWC.
UBWC support for RGB can be had by pretending
that the buffer is BGR.
Signed-off-by: Fritz Koenig
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c| 18 ++
.../drm/msm/disp/dpu1/dpu_hw_catalog_format.h | 2 ++
2 files changed
ct
> drm_encoder *enc,
>
> spin_lock_init(&dpu_enc->enc_spinlock);
>
> - atomic_set(&dpu_enc->frame_done_timeout, 0);
> + atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
> timer_setup(&dpu_enc->frame_done_timer,
>
me_done_timeout_ms, timeout_ms);
> + mod_timer(&dpu_enc->frame_done_timer,
> + jiffies + msecs_to_jiffies(timeout_ms));
> + }
>
> /* All phys encs are ready to go, trigger the kickoff */
> _dpu_encoder_kickoff_phys(dpu_enc, asyn
ingle_flush ||
> !phys->ops.needs_single_flush(phys))
> _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0,
> --
> Sean Paul, Software Engineer, Google / Chromium OS
>
Review
