On Mon, 24 Feb 2025 02:56:15 +0100, Barnabás Czémán wrote:
> This patch series add initial support for MSM8937 SoC
> and Xiaomi Redmi 3S (land).
>
> The series is extending the MSM8917 gcc and pinctrl drivers
> because they are sibling SoCs.
> MSM8937 have 4 more A53 cores and have one more dsi po
From: Rob Clark
Somehow, possibly as a result of rebase gone badly, setting
nr_indexed_regs for pre-a650 a6xx devices lost the setting of
nr_indexed_regs, resulting in values getting snapshot, but omitted
from the devcoredump.
Fixes: e997ae5f45ca ("drm/msm/a6xx: Mostly implement A7xx gpu_state")
then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for
20250228-a623-gpu-support-v2-0-aea654ecc...@quicinc.com:
arch/arm64/boot/dts/qcom/qcs8300-ride.dtb: iommu@3da: clock-names:0:
'
On 28.02.2025 3:40 AM, Dmitry Baryshkov wrote:
> The MSM8937 platform doesn't have DSC blocks nor does have it DSC
> registers in the PINGPONG block. Drop the DPU_PINGPONG_DSC feature bit
> from the PINGPONG's feature mask and, as it is the only remaining bit,
> drop the .features assignment comple
On 28.02.2025 2:43 PM, Konrad Dybcio wrote:
> On 28.02.2025 3:40 AM, Dmitry Baryshkov wrote:
>> The MSM8937 platform doesn't have DSC blocks nor does have it DSC
>> registers in the PINGPONG block. Drop the DPU_PINGPONG_DSC feature bit
>> from the PINGPONG's feature mask and, as it is the only rema
On 28.02.2025 3:40 AM, Dmitry Baryshkov wrote:
> The MSM8937 platform doesn't have DSC blocks nor does have it DSC
> registers in the PINGPONG block. Drop the DPU_PINGPONG_DSC feature bit
> from the PINGPONG's feature mask, replacing PINGPONG_SDM845_MASK and
> PINGPONG_SDM845_TE2_MASK with proper b
On 28.02.2025 3:40 AM, Dmitry Baryshkov wrote:
> The MSM8937 platform doesn't have DSC blocks nor does have it DSC
> registers in the PINGPONG block. Drop the DPU_PINGPONG_DSC feature bit
> from the PINGPONG's feature mask and, as it is the only remaining bit,
> drop the .features assignment comple
On 28.02.2025 3:40 AM, Dmitry Baryshkov wrote:
> The MSM8937 platform doesn't have DSC blocks nor does have it DSC
> registers in the PINGPONG block. Drop the DPU_PINGPONG_DSC feature bit
> from the PINGPONG's feature mask and, as it is the only remaining bit,
> drop the .features assignment comple
On 28.02.2025 3:40 AM, Dmitry Baryshkov wrote:
> The MSM8937 platform doesn't have DSC blocks nor does have it DSC
^
in all patches
Konrad
Dmitry Baryshkov 于2025年2月28日周五 12:39写道：
>
> On Wed, Feb 26, 2025 at 08:31:02PM +0800, Jun Nie wrote:
> > Currently, SSPPs are assigned to a maximum of two pipes. However,
> > quad-pipe usage scenarios require four pipes and involve configuring
> > two stages. In quad-pipe case, the first two pipes
On Fri, Feb 28, 2025 at 01:43:12PM +0530, Akhil P Oommen wrote:
> On 2/28/2025 4:56 AM, Dmitry Baryshkov wrote:
> > On Fri, Feb 28, 2025 at 01:37:51AM +0530, Akhil P Oommen wrote:
> >> From: Jie Zhang
> >>
> >> Add support for Adreno 623 GPU found in QCS8300 chipsets.
> >>
> >> Signed-off-by: Jie
On Fri, Feb 28, 2025 at 10:23:54AM +0100, Marijn Suijten wrote:
> On 28 February 2025 05:14:06 CET, Dmitry Baryshkov
> wrote:
> >If several interfaces are being handled through a single CTL, a main
> >('master') INTF needs to be programmed into a separate register. Write
> >corresponding value in
On 28 February 2025 05:14:12 CET, Dmitry Baryshkov
wrote:
>Now as we have dropped the DPU_CTL_SPLIT_DISPLAY from DPU >= 5.0
>configuration, drop the rm->has_legacy_ctl condition which short-cutted
>the check for those platforms.
>
>Suggested-by: Marijn Suijten
>Signed-off-by: Dmitry Baryshkov
>
On 28 February 2025 05:14:06 CET, Dmitry Baryshkov
wrote:
>If several interfaces are being handled through a single CTL, a main
>('master') INTF needs to be programmed into a separate register. Write
>corresponding value into that register.
>
>Co-developed-by: Marijn Suijten
>Signed-off-by: Mari
On 28/02/2025 05:14, Dmitry Baryshkov wrote:
Since version 5.0 the DPU got an improved way of handling multi-output
configurations. It is now possible to program all pending changes
through a single CTL and flush everything at the same time.
Implement corresponding changes in the DPU driver.
Si
On 2/28/2025 4:56 AM, Dmitry Baryshkov wrote:
> On Fri, Feb 28, 2025 at 01:37:51AM +0530, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add support for Adreno 623 GPU found in QCS8300 chipsets.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>> ---
>> drivers/gpu/drm/msm/adreno
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