If msm_gem_address_space_create() fails, then return right away.
Otherwise it leads to a Oops when we dereference "aspace" on the next
line.
Fixes: 2d215d440faa ("drm/msm: register a fault handler for display mmu faults")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/msm/msm_kms.c | 1 +
1 fi
On 2/13/2025 10:51 PM, Konrad Dybcio wrote:
> On 13.02.2025 5:10 PM, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add support for Adreno 623 GPU found in QCS8300 chipsets.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 2
On 2/18/2025 11:52 PM, Rob Clark wrote:
> On Thu, Feb 13, 2025 at 8:10 AM Akhil P Oommen
> wrote:
>>
>> From: Jie Zhang
>>
>> Adreno 621 has a different memory map for GPUCC block. So update
>> a6xx_gpu_state code to dump the correct set of gpucc registers.
>>
>> Signed-off-by: Jie Zhang
>> Sig
On Mon, 24 Feb 2025 at 20:59, Abhinav Kumar wrote:
>
>
>
> On 2/19/2025 9:08 AM, Dmitry Baryshkov wrote:
> > On Wed, Feb 19, 2025 at 06:02:20PM +0100, Krzysztof Kozlowski wrote:
> >> On 17/02/2025 19:58, Dmitry Baryshkov wrote:
> >>> On Mon, Feb 17, 2025 at 05:41:26PM +0100, Krzysztof Kozlowski wr
On 2/19/2025 9:08 AM, Dmitry Baryshkov wrote:
On Wed, Feb 19, 2025 at 06:02:20PM +0100, Krzysztof Kozlowski wrote:
On 17/02/2025 19:58, Dmitry Baryshkov wrote:
On Mon, Feb 17, 2025 at 05:41:26PM +0100, Krzysztof Kozlowski wrote:
Add DisplayPort controller for Qualcomm SM8750 SoC which so fa
On Fri, 21 Feb 2025 16:24:17 +0100, Krzysztof Kozlowski wrote:
> Add MDSS/MDP display subsystem for Qualcomm SM8750 SoC, next generation
> with two revisions up of the IP block comparing to SM8650.
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> Changes in v3:
> 1. Properly described inter
On Fri, 21 Feb 2025 16:24:15 +0100, Krzysztof Kozlowski wrote:
> Add DisplayPort controller for Qualcomm SM8750 SoC which so far looks
> fully compatible with earlier SM8650 variant - both are of version
> v1.5.1 of the IP block. Datasheet also mentions that both support 4x
> MST for DPTX0 and 2
On Mon, Feb 24, 2025 at 06:14:22PM +0800, Jun Nie wrote:
> Dmitry Baryshkov 于2025年2月22日周六 00:36写道：
> >
> > On Mon, Feb 17, 2025 at 10:16:02PM +0800, Jun Nie wrote:
> > > Currently, SSPPs are assigned to a maximum of two pipes. However,
> > > quad-pipe usage scenarios require four pipes and involve
Dmitry Baryshkov 于2025年2月22日周六 00:36写道：
>
> On Mon, Feb 17, 2025 at 10:16:02PM +0800, Jun Nie wrote:
> > Currently, SSPPs are assigned to a maximum of two pipes. However,
> > quad-pipe usage scenarios require four pipes and involve configuring
> > two stages. In quad-pipe case, the first two pipes
On 12/15/2024 5:10 AM, Dmitry Baryshkov wrote:
Since SmartDMA planes provide two rectangles, it is possible to use them
to drive two different DRM planes, first plane getting the rect_0,
another one using rect_1 of the same SSPP. The sharing algorithm is
pretty simple, it requires that each of
On 2/8/2025 7:21 PM, Dmitry Baryshkov wrote:
Move perf mode handling for the bandwidth to
_dpu_core_perf_crtc_update_bus() rather than overriding per-CRTC data
and then aggregating known values.
Note, this changes the fix_core_ab_vote. Previously it would be
multiplied per the CRTC number, no
From: Dang Huynh
It looks like both 8917 and 8937 are the same except for one pin
"wsa_reset".
Signed-off-by: Dang Huynh
Signed-off-by: Barnabás Czémán
---
drivers/pinctrl/qcom/Kconfig.msm | 4 ++--
drivers/pinctrl/qcom/pinctrl-msm8917.c | 8 +++-
2 files changed, 9 insertions(+), 3
From: Adam Skladowski
Adreno 505 (MSM8937), Adreno 506(MSM8953) and Adreno 510(MSM8976)
require Always-on branch clock to be enabled, describe it.
Signed-off-by: Adam Skladowski
[reword commit, move alwayson on the first place]
Signed-off-by: Barnabás Czémán
---
Documentation/devicetree/bindi
On 2/19/2025 7:59 PM, Dmitry Baryshkov wrote:
Enable the CDM_0 block on DPU generations starting from 5.x as
documented in the vendor dtsi file.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0
Document Xiaomi Redmi 3S (land).
Add qcom,msm8937 for msm-id, board-id allow-list.
Acked-by: Krzysztof Kozlowski
Signed-off-by: Barnabás Czémán
---
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qc
From: Dang Huynh
Add initial support for MSM8937 SoC.
Signed-off-by: Dang Huynh
Co-developed-by: Barnabás Czémán
Signed-off-by: Barnabás Czémán
---
arch/arm64/boot/dts/qcom/msm8937.dtsi | 2149 +
1 file changed, 2149 insertions(+)
diff --git a/arch/arm64/boot
On Sun, 23 Feb 2025 19:57:50 +0100, Barnabás Czémán wrote:
> From: Adam Skladowski
>
> Adreno 505 (MSM8937), Adreno 506(MSM8953) and Adreno 510(MSM8976)
> require Always-on branch clock to be enabled, describe it.
>
> Signed-off-by: Adam Skladowski
> [reword commit, move alwayson on the first
On Sun, 23 Feb 2025 19:57:49 +0100, Barnabás Czémán wrote:
> Add MSM8937 compatible string with "qcom,msm-iommu-v1" as fallback
> for the MSM8937 IOMMU which is compatible with Qualcomm's secure
> fw "SMMU v1" implementation.
>
> Reviewed-by: Krzysztof Kozlowski
> Signed-off-by: Barnabás Czémán
On Sun, 23 Feb 2025 19:57:52 +0100, Barnabás Czémán wrote:
> Document Xiaomi Redmi 3S (land).
> Add qcom,msm8937 for msm-id, board-id allow-list.
>
> Acked-by: Krzysztof Kozlowski
> Signed-off-by: Barnabás Czémán
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++
> 1 file ch
From: Daniil Titov
Modify existing MSM8917 driver to support MSM8937 SoC. Override frequencies
which are different in this chip. Register all the clocks to the framework
for the clients to be able to request for them. Add new variant of GDSC for
new chip.
Signed-off-by: Daniil Titov
Signed-off-
Add initial support for Xiaomi Redmi 3S (land).
Signed-off-by: Barnabás Czémán
---
arch/arm64/boot/dts/qcom/Makefile| 1 +
arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts | 408 +++
2 files changed, 409 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/M
On Sun, 23 Feb 2025 19:57:46 +0100, Barnabás Czémán wrote:
> Add device tree bindings for the global clock controller on Qualcomm
> MSM8937 platform.
>
> Signed-off-by: Barnabás Czémán
> ---
> .../bindings/clock/qcom,gcc-msm8937.yaml | 73
> ++
> include/dt-bindi
Add device tree bindings for the global clock controller on Qualcomm
MSM8937 platform.
Signed-off-by: Barnabás Czémán
---
.../bindings/clock/qcom,gcc-msm8937.yaml | 73 ++
include/dt-bindings/clock/qcom,gcc-msm8917.h | 17 +
2 files changed, 90 insertions(
This patch series add initial support for MSM8937 SoC
and Xiaomi Redmi 3S (land).
The series is extending the MSM8917 gcc and pinctrl drivers
because they are sibling SoCs.
MSM8937 have 4 more A53 cores and have one more dsi port then
MSM8917.
It implements little-big architecture and uses Adreno
Document Xiaomi Redmi 3S (land).
Add qcom,msm8937 for msm-id, board-id allow-list.
Acked-by: Krzysztof Kozlowski
Signed-off-by: Barnabás Czémán
---
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qc
Add MSM8937 compatible string with "qcom,msm-iommu-v1" as fallback
for the MSM8937 IOMMU which is compatible with Qualcomm's secure
fw "SMMU v1" implementation.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Barnabás Czémán
---
Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 1 +
1 f
Add initial support for Xiaomi Redmi 3S (land).
Signed-off-by: Barnabás Czémán
---
arch/arm64/boot/dts/qcom/Makefile| 1 +
arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts | 408 +++
2 files changed, 409 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/M
On Mon, Feb 24, 2025 at 01:38:22PM +0100, Marijn Suijten wrote:
> On 2025-02-21 01:58:58, Dmitry Baryshkov wrote:
> > On Fri, Feb 21, 2025 at 12:34:12AM +0100, Marijn Suijten wrote:
> > > On 2025-02-20 12:26:23, Dmitry Baryshkov wrote:
> > > > Unlike previous generation, since DPU 5.0 it is possibl
On 2025-02-21 01:58:58, Dmitry Baryshkov wrote:
> On Fri, Feb 21, 2025 at 12:34:12AM +0100, Marijn Suijten wrote:
> > On 2025-02-20 12:26:23, Dmitry Baryshkov wrote:
> > > Unlike previous generation, since DPU 5.0 it is possible to use just one
> > > CTL to handle all INTF and WB blocks for a singl
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