On 2025/2/19 20:07, Krzysztof Kozlowski wrote:
On 19/02/2025 11:02, Yongxing Mou wrote:
On 2025/2/12 17:06, Krzysztof Kozlowski wrote:
On 12/02/2025 08:12, Yongxing Mou wrote:
This series of patches introduces how to enable MST functionality on
the qcs8300 platform. The qcs8300 platform u
Enable CDM on the SC8280XP platform, allowing RGB to YUV conversion for
the output.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/d
Enable CDM on the X Elite platform, allowing RGB to YUV conversion for
the output.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dp
Enable the CDM_0 block on DPU versions 1.x - 4.x as
documented in the vendor dtsi file.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_
Enable the CDM_0 block on DPU generations starting from 5.x as
documented in the vendor dtsi file.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/catal
The CDM block is not limited to SC7280, but it is common to all
platforms since DPU 5.x. Rename it from sc7280_cdm to
dpu_cdm_5_x.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog
Enable CDM block on all the platforms where it is supposed to be
present. Notably, from the platforms being supported by the DPU driver
it is not enabled for SM6115 (DPU 6.3), QCM2290 (DPU 6.5) and SM6375
(DPU 6.9)
Signed-off-by: Dmitry Baryshkov
---
Changes in v2:
- Split CDM addition to two pat
On Mon, 17 Feb 2025 17:41:24 +0100, Krzysztof Kozlowski wrote:
> Add DSI PHY v7.0 for Qualcomm SM8750 SoC which is quite different from
> previous (SM8650) generation.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
> 1 file
On 2/17/2025 8:41 AM, Krzysztof Kozlowski wrote:
Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with an
incompatible hardware interface change:
ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
offsets were just switched. Currently these registers are not u
On Mon, 17 Feb 2025 17:41:25 +0100, Krzysztof Kozlowski wrote:
> Add DSI controller for Qualcomm SM8750 SoC which is quite different from
> previous (SM8650) generation.
>
> It does not allow the display clock controller clocks like "byte" and
> "pixel" to be reparented to DSI PHY PLLs while the
On Mon, 17 Feb 2025 17:41:27 +0100, Krzysztof Kozlowski wrote:
> Add DPU for Qualcomm SM8750 SoC which has several differences, new
> blocks and changes in registers, making it incompatible with SM8650.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> Documentation/devicetree/bindings/display/ms
On Mon, Feb 17, 2025 at 05:41:28PM +0100, Krzysztof Kozlowski wrote:
> Add MDSS/MDP display subsystem for Qualcomm SM8750 SoC, next generation
> with two revisions up of the IP block comparing to SM8650.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> .../bindings/display/msm/qcom,sm8750-mdss.yam
On Mon, 17 Feb 2025 17:41:22 +0100, Krzysztof Kozlowski wrote:
> Several devices have the same clock inputs, thus they can be in the same
> if:then: clause, making everything smaller. No functional impact.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> .../bindings/display/msm/dsi-controller-
On Mon, 17 Feb 2025 17:41:23 +0100, Krzysztof Kozlowski wrote:
> Specific constrain in if:then: blocks for variable lists, like clocks
> and clock-names, should have a fixed upper and lower size. Older
> dtschema implied minItems, but that's not true since 2024 and missing
> minItems means that
On Wed, Feb 19, 2025 at 01:17:35PM -0800, Jessica Zhang wrote:
>
>
> On 2/17/2025 8:41 AM, Krzysztof Kozlowski wrote:
> > Hi,
> >
> > Dependency / Rabased on top of:
> > https://lore.kernel.org/all/20241214-dpu-drop-features-v1-0-988f0662c...@linaro.org/
> >
> > Changes in v2:
> > - Implement L
On 2/17/2025 8:41 AM, Krzysztof Kozlowski wrote:
MDSS/MDP v12 comes with new bits in flush registers (e.g.
MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7.
Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++
1 file changed
On 2/17/2025 8:41 AM, Krzysztof Kozlowski wrote:
Drop comments about SoC before each 'struct dpu_lm_sub_blks' for given
SoC because it's duplicating the actual name of structure.
Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cat
On 2/17/2025 8:41 AM, Krzysztof Kozlowski wrote:
Add IDs for new blocks present in MDSS/MDP v12 for LM, DSC, PINGPONG and
MERGE_3D blocks.
Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 6 ++
1 file changed, 6 inser
On 2/17/2025 8:41 AM, Krzysztof Kozlowski wrote:
Add IDs for new blocks present in MDSS/MDP v12 for LM, DSC, PINGPONG and
MERGE_3D blocks.
Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 6 ++
1 file changed, 6 inser
On 2/17/2025 8:41 AM, Krzysztof Kozlowski wrote:
Hi,
Dependency / Rabased on top of:
https://lore.kernel.org/all/20241214-dpu-drop-features-v1-0-988f0662c...@linaro.org/
Changes in v2:
- Implement LM crossbar, 10-bit alpha and active layer changes:
New patch: drm/msm/dpu: Implement new v1
On Wed, Feb 19, 2025 at 11:49:21AM -0800, Jessica Zhang wrote:
> From: Abhinav Kumar
>
> There is no recovery mechanism in place yet to recover from mmu
> faults for DPU. We can only prevent the faults by making sure there
> is no misconfiguration.
>
> Rate-limit the snapshot capture for mmu fau
On 2/18/2025 8:07 PM, Haoxiang Li wrote:
Add check for the return value of devm_kstrdup() in
dsi_host_parse_dt() to catch potential exception.
Fixes: 958d8d99ccb3 ("drm/msm/dsi: parse vsync source from device tree")
Cc: sta...@vger.kernel.org
Signed-off-by: Haoxiang Li
---
drivers/gpu/drm/
From: Abhinav Kumar
Introduce a new API msm_iommu_disp_new() for display use-cases.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_iommu.c | 26 ++
drivers/gpu/drm/msm/msm_mmu.h | 1 +
2 files cha
From: Abhinav Kumar
Switch msm_kms to use msm_iommu_disp_new() so that the newly
registered fault handler will kick-in during any mmu faults.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_kms.c | 2 +-
1 file changed, 1 in
From: Abhinav Kumar
In preparation to register a iommu fault handler for display
related modules, register a fault handler for the backing
mmu object of msm_kms.
Currently, the fault handler only captures the display snapshot
but we can expand this later if more information needs to be
added to
To debug display mmu faults, this series introduces a display fault
handler similar to the gpu one.
This series has been tested on sc7280 chromebook by using triggering
a smmu fault by forcing an incorrect stride on the planes.
---
Changes in v3:
- Move resetting of fault_snapshot_capture to befo
From: Abhinav Kumar
In preparation of registering a separate fault handler for
display, lets rename the existing msm_fault_handler to
msm_gpu_fault_handler.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_iommu.c | 6 +++---
From: Abhinav Kumar
There is no recovery mechanism in place yet to recover from mmu
faults for DPU. We can only prevent the faults by making sure there
is no misconfiguration.
Rate-limit the snapshot capture for mmu faults to once per
msm_atomic_commit_tail() as that should be sufficient to capt
On Wed, Feb 19, 2025 at 05:23:33PM +0100, Krzysztof Kozlowski wrote:
> Add bitfields for PHY_CMN_CLK_CFG0 and PHY_CMN_CLK_CFG1 registers to
> avoid hard-coding bit masks and shifts and make the code a bit more
> readable.
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> Changes in v5:
> 1. Sp
On Wed, Feb 19, 2025 at 06:02:20PM +0100, Krzysztof Kozlowski wrote:
> On 17/02/2025 19:58, Dmitry Baryshkov wrote:
> > On Mon, Feb 17, 2025 at 05:41:26PM +0100, Krzysztof Kozlowski wrote:
> >> Add DisplayPort controller for Qualcomm SM8750 SoC which so far looks
> >> fully compatible with earlier
On Wed, 19 Feb 2025 at 19:04, Krzysztof Kozlowski
wrote:
>
> On 17/02/2025 20:18, Dmitry Baryshkov wrote:
> > On Mon, Feb 17, 2025 at 05:41:36PM +0100, Krzysztof Kozlowski wrote:
> >> Implement new features and differences coming in v12.0 of DPU present on
> >> Qualcomm SM8750 SoC:
> >> 1. 10-bit
On Wed, Feb 19, 2025 at 05:23:32PM +0100, Krzysztof Kozlowski wrote:
> Newly added dsi_pll_cmn_clk_cfg1_update() wrapper protects concurrent
> updates to PHY_CMN_CLK_CFG1 register between driver and Common Clock
> Framework. pll_7nm_register() still used in one place previous
> readl+writel, which
On 17/02/2025 20:18, Dmitry Baryshkov wrote:
> On Mon, Feb 17, 2025 at 05:41:36PM +0100, Krzysztof Kozlowski wrote:
>> Implement new features and differences coming in v12.0 of DPU present on
>> Qualcomm SM8750 SoC:
>> 1. 10-bit color alpha.
>> 2. New CTL_PIPE_ACTIVE and CTL_LAYER_ACTIVE registers
On 17/02/2025 19:58, Dmitry Baryshkov wrote:
> On Mon, Feb 17, 2025 at 05:41:26PM +0100, Krzysztof Kozlowski wrote:
>> Add DisplayPort controller for Qualcomm SM8750 SoC which so far looks
>> fully compatible with earlier SM8650 variant.
>
> As that became a question for QCS8300, does SM8750 also
Changes in v5:
- Drop applied patches 1-3
- Split part touching pll_7nm_register() from last (#4) patch to new patch
- Thus: new patch #1 in new numbering.
- Link to v4:
https://lore.kernel.org/r/20250217-drm-msm-phy-pll-cfg-reg-v4-0-106b0d1df...@linaro.org
Changes in v4:
- Add tags
- Patch #4
Add bitfields for PHY_CMN_CLK_CFG0 and PHY_CMN_CLK_CFG1 registers to
avoid hard-coding bit masks and shifts and make the code a bit more
readable.
Signed-off-by: Krzysztof Kozlowski
---
Changes in v5:
1. Split part touching pll_7nm_register() to new patch.
2. Update commit msg.
Changes in v4:
Newly added dsi_pll_cmn_clk_cfg1_update() wrapper protects concurrent
updates to PHY_CMN_CLK_CFG1 register between driver and Common Clock
Framework. pll_7nm_register() still used in one place previous
readl+writel, which can be simplified with this new wrapper.
This is purely for readability and
Add check for the return value of devm_kstrdup() in
dsi_host_parse_dt() to catch potential exception.
Fixes: 958d8d99ccb3 ("drm/msm/dsi: parse vsync source from device tree")
Cc: sta...@vger.kernel.org
Signed-off-by: Haoxiang Li
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 9 -
1 file change
The MSM DisplayPort driver implements several HDMI codec functions
in the driver, e.g. it manually manages HDMI codec device registration,
returning ELD and plugged_cb support. In order to reduce code
duplication reuse drm_hdmi_audio_* helpers and drm_bridge_connector
integration.
As a part of thi
A lot of DisplayPort bridges use HDMI Codec in order to provide audio
support. Present DRM HDMI Audio support has been written with the HDMI
and in particular DRM HDMI Connector framework support, however those
audio helpers can be easily reused for DisplayPort drivers too.
Patches by Hermes Wu th
As pointed out by Laurent, OP bits are supposed to describe operations.
Split DRM_BRIDGE_OP_HDMI_AUDIO from DRM_BRIDGE_OP_HDMI instead of
overloading DRM_BRIDGE_OP_HDMI.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/lontium-lt9611.c| 2 +-
drivers/gpu/drm/display/drm_bridge
On Wed, Feb 19, 2025 at 05:56:14PM +0800, Yongxing Mou wrote:
>
>
> On 2025/2/12 20:26, Dmitry Baryshkov wrote:
> > On Wed, 12 Feb 2025 at 12:54, Krzysztof Kozlowski wrote:
> > >
> > > On 12/02/2025 11:41, Dmitry Baryshkov wrote:
> > > > On Wed, Feb 12, 2025 at 03:12:24PM +0800, Yongxing Mou wr
On Wed, Feb 19, 2025 at 12:07:12PM +0800, Haoxiang Li wrote:
> Add check for the return value of devm_kstrdup() in
> dsi_host_parse_dt() to catch potential exception.
>
> Fixes: 958d8d99ccb3 ("drm/msm/dsi: parse vsync source from device tree")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Haoxiang
On 19/02/2025 11:02, Yongxing Mou wrote:
>
>
> On 2025/2/12 17:06, Krzysztof Kozlowski wrote:
>> On 12/02/2025 08:12, Yongxing Mou wrote:
>>> This series of patches introduces how to enable MST functionality on
>>> the qcs8300 platform. The qcs8300 platform uses dpu_8_4 hardware, which
>>> is the
On Wed, Feb 19, 2025 at 06:02:27PM +0800, Yongxing Mou wrote:
>
>
> On 2025/2/12 17:06, Krzysztof Kozlowski wrote:
> > On 12/02/2025 08:12, Yongxing Mou wrote:
> > > This series of patches introduces how to enable MST functionality on
> > > the qcs8300 platform. The qcs8300 platform uses dpu_8_4
On 2025/2/12 18:51, Dmitry Baryshkov wrote:
On Wed, Feb 12, 2025 at 03:12:23PM +0800, Yongxing Mou wrote:
This series of patches introduces how to enable MST functionality on
the qcs8300 platform.
The qcs8300 platform uses dpu_8_4 hardware, which
is the same as the sa8775p, but it only has
On 2025/2/12 18:42, Dmitry Baryshkov wrote:
On Wed, Feb 12, 2025 at 03:12:24PM +0800, Yongxing Mou wrote:
We need to enable mst for qcs8300, dp0 controller will support 2 streams
output. So not reuse sm8650 dp controller driver and will add a new driver
patch for qcs8300 mst feature. Modify t
On 2025/2/12 17:06, Krzysztof Kozlowski wrote:
On 12/02/2025 08:12, Yongxing Mou wrote:
This series of patches introduces how to enable MST functionality on
the qcs8300 platform. The qcs8300 platform uses dpu_8_4 hardware, which
is the same as the sa8775p, but it only has one DPU. So it only
On 2025/2/13 7:41, Konrad Dybcio wrote:
On 12.02.2025 8:12 AM, Yongxing Mou wrote:
Add 2 streams MST support for qcs8300. Compatile with qcs8300 dp
controller driver and populate the stream clock for qcs8300 DP0
controller in MST mode.
Signed-off-by: Yongxing Mou
---
Please add all requir
On 2025/2/12 16:34, Krzysztof Kozlowski wrote:
Your patchset leads to warnings - it is non-bisectable.
Fix original code, don't post buggy patches just to fix them immediately.
Got it. Thanks for the reminder, won't do it again.
On 2025/2/12 20:26, Dmitry Baryshkov wrote:
On Wed, 12 Feb 2025 at 12:54, Krzysztof Kozlowski wrote:
On 12/02/2025 11:41, Dmitry Baryshkov wrote:
On Wed, Feb 12, 2025 at 03:12:24PM +0800, Yongxing Mou wrote:
We need to enable mst for qcs8300, dp0 controller will support 2 streams
output.
On 2025/2/12 21:44, Konrad Dybcio wrote:
On 12.02.2025 12:28 PM, Krzysztof Kozlowski wrote:
On 12/02/2025 12:13, Yongxing Mou wrote:
On 2025/2/12 16:35, Krzysztof Kozlowski wrote:
On 12/02/2025 08:12, Yongxing Mou wrote:
We need to enable mst for qcs8300, dp0 controller will support 2 st
On 2025/2/12 19:28, Krzysztof Kozlowski wrote:
On 12/02/2025 12:13, Yongxing Mou wrote:
On 2025/2/12 16:35, Krzysztof Kozlowski wrote:
On 12/02/2025 08:12, Yongxing Mou wrote:
We need to enable mst for qcs8300, dp0 controller will support 2 streams
output. So not reuse sm8650 dp controlle
Hi
Am 18.02.25 um 16:57 schrieb Russell King (Oracle):
On Tue, Feb 18, 2025 at 03:23:29PM +0100, Thomas Zimmermann wrote:
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. No alignment required.
Signed-off-by: Thomas Zimmermann
Cc: Russell King
armada_pitch()
Hi
Am 18.02.25 um 20:32 schrieb Geert Uytterhoeven:
[...]
+args->bpp);
+ fallthrough;
+ case 12:
+ case 15:
+ case 30: /* see drm_gem_afbc_get_bpp() */
+ case 10:
Perhaps keep them sort
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