On 2/12/2025 5:30 AM, Dmitry Baryshkov wrote:
> On Tue, Feb 11, 2025 at 06:41:39PM +0530, Akhil P Oommen wrote:
>> On 2/9/2025 9:59 PM, Dmitry Baryshkov wrote:
>>> On Wed, Nov 13, 2024 at 02:18:43AM +0530, Akhil P Oommen wrote:
On 10/30/2024 12:32 PM, Akhil P Oommen wrote:
> From: Puranam
Add 2 streams MST support for qcs8300. Compatile with qcs8300 dp
controller driver and populate the stream clock for qcs8300 DP0
controller in MST mode.
Signed-off-by: Yongxing Mou
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff
Add support to program 2 streams MST for qcs8300. Previously, the
qcs8300 reused the driver of the sm8650's DP controller because they
have the same base address, offset, and number of controllers. However,
now we need to enable the MST feature for the qcs8300, so we need a new
patch The qcs8300 us
Support mst for qcs8300 and add the stream 1 clock support in the mdss
dt-bindings.
Signed-off-by: Yongxing Mou
---
.../devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git
a/Documentation/devicetree/bindings/dis
We need to enable mst for qcs8300, dp0 controller will support 2 streams
output. So not reuse sm8650 dp controller driver and will add a new driver
patch for qcs8300 mst feature. Modify the corresponding dt-bingding file
to compatible with the qcs8300-dp.
Signed-off-by: Yongxing Mou
---
Document
/dp/dp_display.c| 8
4 files changed, 25 insertions(+), 14 deletions(-)
---
base-commit: 7ba9bcc5090556c007d9a718d7176e097fe54f19
change-id: 20250211-mst_qcs8300-4c18a5179165
Best regards,
--
Yongxing Mou
Hello,
we noticed the issue happens with a low rate on this commit, but keeps clean
on parent when we even run the tests up to 999 times. just FYI.
41f70d8e16349c65 b04e317b522630b46f78ee62ecb
---
fail:runs %reproductionfail:runs
r(phys_enc->hw_pp, NULL);
+
/* reset the merge 3D HW block */
if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) {
phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
---
base-commit: 866e43b945bf98f8e807dfa45eca92
On 2/11/2025 4:13 PM, Dmitry Baryshkov wrote:
On Tue, Feb 11, 2025 at 10:23:54AM +0100, Marijn Suijten wrote:
On 2025-02-10 14:14:14, Abhinav Kumar wrote:
On 2/9/2025 7:51 PM, Ethan Carter Edwards wrote:
There is a possibility for an uninitialized *ret* variable to be
returned in some cod
On Tue, Feb 11, 2025 at 09:26:31AM +0100, Krzysztof Kozlowski wrote:
> On Sun, Feb 09, 2025 at 07:04:46AM +0200, Dmitry Baryshkov wrote:
> > Supporting simultaneous check of native HPD and the external GPIO proved
> > to be less stable than just native HPD. Drop the hpd-gpios from the
> > bindings.
On Tue, Feb 11, 2025 at 10:23:54AM +0100, Marijn Suijten wrote:
> On 2025-02-10 14:14:14, Abhinav Kumar wrote:
> >
> >
> > On 2/9/2025 7:51 PM, Ethan Carter Edwards wrote:
> > > There is a possibility for an uninitialized *ret* variable to be
> > > returned in some code paths.
> > >
> > > Fix th
topology.num_dspp = topology.num_lm;
>
> ---
> base-commit: df5d6180169ae06a2eac57e33b077ad6f6252440
> change-id: 20250211-dp_lm-8f8ef15f5955
>
> Best regards,
> --
> Yongxing Mou
>
--
With best wishes
Dmitry
On Tue, Feb 11, 2025 at 10:07:07AM +0100, Neil Armstrong wrote:
> On 10/02/2025 17:32, Konrad Dybcio wrote:
> > On 10.02.2025 10:32 AM, Neil Armstrong wrote:
> > > The bindings requires the mdp0-mem and the cpu-cfg interconnect path,
> > > add the missing cpu-cfg path to fix the dtbs check error.
>
On Tue, Feb 11, 2025 at 06:41:39PM +0530, Akhil P Oommen wrote:
> On 2/9/2025 9:59 PM, Dmitry Baryshkov wrote:
> > On Wed, Nov 13, 2024 at 02:18:43AM +0530, Akhil P Oommen wrote:
> >> On 10/30/2024 12:32 PM, Akhil P Oommen wrote:
> >>> From: Puranam V G Tejaswi
> >>>
> >>> Enable GPU for sa8775p-r
On Tue, Feb 11, 2025 at 02:31:14PM +0100, Konrad Dybcio wrote:
> On 3.02.2025 7:14 PM, Danila Tikhonov wrote:
> > From: Eugene Lepshy
> >
> > Enable the Adreno GPU and configure the Visionox RM692E5 panel.
> >
> > Signed-off-by: Eugene Lepshy
> > Co-developed-by: Danila Tikhonov
> > Signed-off
On Tue, Feb 11, 2025 at 09:06:19PM +0300, Danila Tikhonov wrote:
> On 2/9/25 01:09, Marijn Suijten wrote:
> > On 2025-02-03 21:14:26, Danila Tikhonov wrote:
> > > From: Eugene Lepshy
> > >
> > > DRM DSC helper has parameters for various bpc values other than 8:
> > Weird zero-width \u200b space
On 2/9/25 01:09, Marijn Suijten wrote:
On 2025-02-03 21:14:26, Danila Tikhonov wrote:
From: Eugene Lepshy
DRM DSC helper has parameters for various bpc values other than 8:
Weird zero-width \u200b spaces here between "values" and "other", please delete
those.
Thanks, I will fix it in the n
On Tue, Feb 11, 2025 at 12:14:23PM +0100, Philipp Stanner wrote:
> drm_sched_init() has a great many parameters and upcoming new
> functionality for the scheduler might add even more. Generally, the
> great number of parameters reduces readability and has already caused
> one missnaming, addressed
On 3.02.2025 7:14 PM, Danila Tikhonov wrote:
> From: Eugene Lepshy
>
> Enable the Adreno GPU and configure the Visionox RM692E5 panel.
>
> Signed-off-by: Eugene Lepshy
> Co-developed-by: Danila Tikhonov
> Signed-off-by: Danila Tikhonov
> ---
> Note:
> Depends on
> https://lore.kernel.org/lin
On 2/9/2025 9:59 PM, Dmitry Baryshkov wrote:
> On Wed, Nov 13, 2024 at 02:18:43AM +0530, Akhil P Oommen wrote:
>> On 10/30/2024 12:32 PM, Akhil P Oommen wrote:
>>> From: Puranam V G Tejaswi
>>>
>>> Enable GPU for sa8775p-ride platform and provide path for zap
>>> shader.
>>>
>>> Signed-off-by: Pur
On 11.02.2025 10:07 AM, Neil Armstrong wrote:
> On 10/02/2025 17:32, Konrad Dybcio wrote:
>> On 10.02.2025 10:32 AM, Neil Armstrong wrote:
>>> The bindings requires the mdp0-mem and the cpu-cfg interconnect path,
>>> add the missing cpu-cfg path to fix the dtbs check error.
>>>
>>> Fixes: b8591df49
drm_sched_init() has a great many parameters and upcoming new
functionality for the scheduler might add even more. Generally, the
great number of parameters reduces readability and has already caused
one missnaming, addressed in:
commit 6f1cacf4eba7 ("drm/nouveau: Improve variable name in
nouveau_
topology.num_lm = (mode->hdisplay >
dpu_kms->catalog->caps->max_mixer_width) ?
+ 2 : 1;
if (crtc_state->ctm)
topology.num_dspp = topology.num_lm;
---
base-commit: df5d6180169ae06a2eac57e33b077ad6f6252440
change-id: 20250211
On 2025-02-10 14:14:14, Abhinav Kumar wrote:
>
>
> On 2/9/2025 7:51 PM, Ethan Carter Edwards wrote:
> > There is a possibility for an uninitialized *ret* variable to be
> > returned in some code paths.
> >
> > Fix this by initializing *ret* to 0.
> >
> > Addresses-Coverity-ID: 1642546 ("Uniniti
On 10/02/2025 17:32, Konrad Dybcio wrote:
On 10.02.2025 10:32 AM, Neil Armstrong wrote:
The bindings requires the mdp0-mem and the cpu-cfg interconnect path,
add the missing cpu-cfg path to fix the dtbs check error.
Fixes: b8591df49cde ("arm64: dts: qcom: sm8550: correct MDSS interconnects")
Si
On Mon, Feb 10, 2025 at 10:32:40AM +0100, Neil Armstrong wrote:
> The mdp1-mem is not supported on the SM8550 SoCs, and having maxItems=2
> makes the bindings not clear if mdp0-mem/mdp1-mem or mdp0-mem/cpu-cfg
> is required, so explicitly document the mdp0-mem/cpu-cfg interconnect
> paths and compl
On Mon, Feb 10, 2025 at 10:32:39AM +0100, Neil Armstrong wrote:
> The mdp1-mem is not supported on the SM8550 SoCs, and having maxItems=2
> makes the bindings not clear if mdp0-mem/mdp1-mem or mdp0-mem/cpu-cfg is
> required, so explicitly document the mdp0-mem/cpu-cfg interconnect and
> add the cpu
On Sun, Feb 09, 2025 at 07:04:45AM +0200, Dmitry Baryshkov wrote:
> The commit 68e674b13b17 ("drm/msm/hdmi: drop unused GPIO support")
That commit looks a lot like an ABI break and keeping bindings is a
proof of that. Commit mentions upstreamed platforms, but you have also
downstream users which
On Sun, Feb 09, 2025 at 07:04:46AM +0200, Dmitry Baryshkov wrote:
> Supporting simultaneous check of native HPD and the external GPIO proved
> to be less stable than just native HPD. Drop the hpd-gpios from the
> bindings. This is not a breaking change, since the HDMI block has been
> using both GP
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