On Thu, Feb 06, 2025 at 12:41:30PM -0800, Abhinav Kumar wrote:
>
>
> On 2/3/2025 4:59 PM, Dmitry Baryshkov wrote:
> > On Mon, Feb 03, 2025 at 11:34:00AM -0800, Abhinav Kumar wrote:
> > >
> > >
> > > On 1/24/2025 1:47 PM, Dmitry Baryshkov wrote:
> > > > The mode_set callback is deprecated, it do
On Thu, Feb 06, 2025 at 02:45:19PM -0800, Jessica Zhang wrote:
>
>
> On 1/29/2025 9:51 AM, Dmitry Baryshkov wrote:
> > On Tue, Jan 28, 2025 at 07:20:32PM -0800, Jessica Zhang wrote:
> > > DPU supports a single writeback session running concurrently with primary
> > > display when the CWB mux is c
On 1/17/2025 8:00 AM, Jun Nie wrote:
Currently if DSC support is requested, the driver only supports using
2 DSC blocks. We need 4 DSC in quad-pipe topology in future. So Only
configure DSC engines in use, instead of the maximum number of DSC
engines.
Signed-off-by: Jun Nie
Reviewed-by: Dmit
On 1/17/2025 8:00 AM, Jun Nie wrote:
Currently, if DSC is enabled, only 2 DSC engines are supported so far.
More usage cases will be added, such as 4 DSC in 4:4:2 topology. So
get the real number of DSCs to decide whether DSC merging is needed.
Signed-off-by: Jun Nie
Reviewed-by: Dmitry Bary
On Thu, Feb 06, 2025 at 03:49:53PM -0800, Jessica Zhang wrote:
>
>
> On 1/29/2025 2:04 PM, Dmitry Baryshkov wrote:
> > On Tue, Jan 28, 2025 at 07:20:34PM -0800, Jessica Zhang wrote:
> > > From: Dmitry Baryshkov
> > >
> > > All resource allocation is centered around the LMs. Then other blocks
>
On Thu, Feb 06, 2025 at 11:46:36AM -0800, Abhinav Kumar wrote:
> Widebus allows the DP controller to operate in 2 pixel per clock mode.
> The mode validation logic validates the mode->clock against the max
> DP pixel clock. However the max DP pixel clock limit assumes widebus
> is already enabled.
On 1/29/2025 2:04 PM, Dmitry Baryshkov wrote:
On Tue, Jan 28, 2025 at 07:20:34PM -0800, Jessica Zhang wrote:
From: Dmitry Baryshkov
All resource allocation is centered around the LMs. Then other blocks
(except DSCs) are allocated basing on the LMs that was selected, and LM
powers up the CRT
On 1/29/2025 9:51 AM, Dmitry Baryshkov wrote:
On Tue, Jan 28, 2025 at 07:20:32PM -0800, Jessica Zhang wrote:
DPU supports a single writeback session running concurrently with primary
display when the CWB mux is configured properly. This series enables
clone mode for DPU driver and adds suppor
On 2/3/2025 4:59 PM, Dmitry Baryshkov wrote:
On Mon, Feb 03, 2025 at 11:34:00AM -0800, Abhinav Kumar wrote:
On 1/24/2025 1:47 PM, Dmitry Baryshkov wrote:
The mode_set callback is deprecated, it doesn't get the
drm_bridge_state, just mode-related argumetns. Also Abhinav pointed out
that HDM
Widebus allows the DP controller to operate in 2 pixel per clock mode.
The mode validation logic validates the mode->clock against the max
DP pixel clock. However the max DP pixel clock limit assumes widebus
is already enabled. Adjust the mode validation logic to only compare
the adjusted pixel clo
Hi,
On 03/02/2025 19:14, Danila Tikhonov wrote:
From: Eugene Lepshy
Add the driver for Visionox RM692E5 panel support found in Nothing
Phone (1).
Signed-off-by: Eugene Lepshy
Co-developed-by: Danila Tikhonov
Signed-off-by: Danila Tikhonov
---
drivers/gpu/drm/panel/Kconfig
The MSM DisplayPort driver implements several HDMI codec functions
in the driver, e.g. it manually manages HDMI codec device registration,
returning ELD and plugged_cb support. In order to reduce code
duplication reuse drm_hdmi_audio_* helpers and drm_bridge_connector
integration.
Signed-off-by: D
deletions(-)
---
base-commit: 93c7dd1b39444ebd5a6a98e56a363d7a4e646775
change-id: 20250206-dp-hdmi-audio-15d9fdbebb9f
Best regards,
--
Dmitry Baryshkov
DRM HDMI Codec framework is useful not only for the HDMI bridges, but
also for the DisplayPort bridges. Add new DRM_BRIDGE_OP_DisplayPort
define in order to distinguish DP bridges. Create HDMI codec device
automatically for DP bridges which have declared audio support.
Note, unlike HDMI devices, w
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