Re: [PATCH v5 03/14] drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation

On Tue, Jan 28, 2025 at 07:20:35PM -0800, Jessica Zhang wrote: > From: Dmitry Baryshkov > > Up to now the driver has been using encoder to allocate hardware > resources. Switch it to use CRTC id in preparation for the next step. > > Reviewed-by: Abhinav Kumar > Signed-off-by: Dmitry Baryshkov

Re: [PATCH v5 07/14] drm/msm/dpu: Reserve resources for CWB

On Tue, Jan 28, 2025 at 07:20:39PM -0800, Jessica Zhang wrote: > Add support for RM to reserve dedicated CWB PINGPONGs and CWB muxes > > For concurrent writeback, even-indexed CWB muxes must be assigned to > even-indexed LMs and odd-indexed CWB muxes for odd-indexed LMs. The same > even/odd rule a

Re: [PATCH v5 06/14] drm/msm/dpu: Fail atomic_check if multiple outputs request CDM block

On Tue, Jan 28, 2025 at 07:20:38PM -0800, Jessica Zhang wrote: > Currently, our hardware only supports a single output using CDM block at > most. Because of this, we cannot support cases where both writeback and DP > output request CDM simultaneously > > To avoid this happening when CWB is enabled

Re: [PATCH v5 02/14] drm/msm/dpu: move resource allocation to CRTC

On Tue, Jan 28, 2025 at 07:20:34PM -0800, Jessica Zhang wrote: > From: Dmitry Baryshkov > > All resource allocation is centered around the LMs. Then other blocks > (except DSCs) are allocated basing on the LMs that was selected, and LM > powers up the CRTC rather than the encoder. > > Moreover i

Re: [PATCH v5 00/14] drm/msm/dpu: Add Concurrent Writeback Support for DPU 10.x+

On Tue, Jan 28, 2025 at 07:20:32PM -0800, Jessica Zhang wrote: > DPU supports a single writeback session running concurrently with primary > display when the CWB mux is configured properly. This series enables > clone mode for DPU driver and adds support for programming the CWB mux > in cases where

Re: [PATCH v2] drm/sched: Use struct for drm_sched_init() params

On Wed, Jan 29, 2025 at 04:18:30PM +0100, Philipp Stanner wrote: > On Tue, 2025-01-28 at 15:56 +0100, Danilo Krummrich wrote: > > On Tue, Jan 28, 2025 at 03:29:27PM +0100, Philipp Stanner wrote: > > > diff --git a/drivers/gpu/drm/nouveau/nouveau_sched.c > > > b/drivers/gpu/drm/nouveau/nouveau_sched

Re: [PATCH v3 1/3] iommu/arm-smmu: Fix spurious interrupts with stall-on-fault

On Tue, Jan 28, 2025 at 7:34 PM Connor Abbott wrote: > > On Tue, Jan 28, 2025 at 10:25 PM Rob Clark wrote: > > > > On Tue, Jan 28, 2025 at 6:31 PM Connor Abbott wrote: > > > > > > On Tue, Jan 28, 2025 at 9:21 PM Rob Clark wrote: > > > > > > > > On Tue, Jan 28, 2025 at 2:15 PM Connor Abbott >

Re: [PATCH v2] drm/sched: Use struct for drm_sched_init() params

On Tue, 2025-01-28 at 15:56 +0100, Danilo Krummrich wrote: > On Tue, Jan 28, 2025 at 03:29:27PM +0100, Philipp Stanner wrote: > > drm_sched_init() has a great many parameters and upcoming new > > functionality for the scheduler might add even more. Generally, the > > great number of parameters redu

Re: [PATCH v2] drm/sched: Use struct for drm_sched_init() params

Hi Philipp, On 29/01/25 09:39, Philipp Stanner wrote: On Wed, 2025-01-29 at 07:53 -0300, Maíra Canal wrote: Hi Philipp, On 28/01/25 11:29, Philipp Stanner wrote: drm_sched_init() has a great many parameters and upcoming new functionality for the scheduler might add even more. Generally, the g

Re: [PATCH RFC] drm/msm/dsi/phy: Program clock inverters in correct register

On 29/01/2025 15:31, Dmitry Baryshkov wrote: > On Wed, Jan 29, 2025 at 12:55:04PM +0100, Krzysztof Kozlowski wrote: >> Since SM8250 all downstream sources program clock inverters in >> PLL_CLOCK_INVERTERS_1 register and leave the PLL_CLOCK_INVERTERS as >> reset value (0x0). The most recent Hardwar

Re: [PATCH RFC] drm/msm/dsi/phy: Program clock inverters in correct register

On Wed, Jan 29, 2025 at 12:55:04PM +0100, Krzysztof Kozlowski wrote: > Since SM8250 all downstream sources program clock inverters in > PLL_CLOCK_INVERTERS_1 register and leave the PLL_CLOCK_INVERTERS as > reset value (0x0). The most recent Hardware Programming Guide for 3 nm, > 4 nm, 5 nm and 7 n

Re: [PATCH v2] drm/sched: Use struct for drm_sched_init() params

On Wed, 2025-01-29 at 07:53 -0300, Maíra Canal wrote: > Hi Philipp, > > On 28/01/25 11:29, Philipp Stanner wrote: > > drm_sched_init() has a great many parameters and upcoming new > > functionality for the scheduler might add even more. Generally, the > > great number of parameters reduces readabi

[PATCH RFC] drm/msm/dsi/phy: Program clock inverters in correct register

Since SM8250 all downstream sources program clock inverters in PLL_CLOCK_INVERTERS_1 register and leave the PLL_CLOCK_INVERTERS as reset value (0x0). The most recent Hardware Programming Guide for 3 nm, 4 nm, 5 nm and 7 nm PHYs also mention PLL_CLOCK_INVERTERS_1. Signed-off-by: Krzysztof Kozlowsk

Re: [PATCH v2] drm/sched: Use struct for drm_sched_init() params

Hi Philipp, On 28/01/25 11:29, Philipp Stanner wrote: drm_sched_init() has a great many parameters and upcoming new functionality for the scheduler might add even more. Generally, the great number of parameters reduces readability and has already caused one missnaming in: commit 6f1cacf4eba7 ("

Re: [PATCH v2] drm/sched: Use struct for drm_sched_init() params

On Tue, 28 Jan 2025 15:29:27 +0100 Philipp Stanner wrote: > drm_sched_init() has a great many parameters and upcoming new > functionality for the scheduler might add even more. Generally, the > great number of parameters reduces readability and has already caused > one missnaming in: > > commit

Re: [PATCH v2] drm/sched: Use struct for drm_sched_init() params

> > drm_sched_init() has a great many parameters and upcoming new > functionality for the scheduler might add even more. Generally, the > great number of parameters reduces readability and has already caused > one missnaming in: > > commit 6f1cacf4eba7 ("drm/nouveau: Improve variable name in > nou