On Wed, Jan 22, 2025 at 06:04:58PM +0100, Boris Brezillon wrote:
> On Wed, 22 Jan 2025 16:14:59 +
> Tvrtko Ursulin wrote:
>
> > On 22/01/2025 15:51, Boris Brezillon wrote:
> > > On Wed, 22 Jan 2025 15:08:20 +0100
> > > Philipp Stanner wrote:
> > >
> > >> --- a/drivers/gpu/drm/panthor/pant
On 12/13/2024 2:14 PM, Dmitry Baryshkov wrote:
Continue migration to the MDSS-revision based checks and replace
DPU_DATA_HCTL_EN feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/
On 12/13/2024 2:14 PM, Dmitry Baryshkov wrote:
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_VM_CFG feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8 ++--
drivers
On 12/13/2024 2:14 PM, Dmitry Baryshkov wrote:
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_DSPP_SUB_BLOCK_FLUSH feature bit with the core_major_ver >= 7
check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/
On 12/13/2024 2:14 PM, Dmitry Baryshkov wrote:
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_FETCH_ACTIVE feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/
On 1/22/2025 1:53 AM, Dmitry Baryshkov wrote:
On Tue, Jan 21, 2025 at 04:58:03PM -0800, Abhinav Kumar wrote:
On 12/13/2024 2:14 PM, Dmitry Baryshkov wrote:
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check.
S
On Fri, Jan 17, 2025 at 10:56:35AM +0200, Dmitry Baryshkov wrote:
> Existing DPCD access functions return an error code or the number of
> bytes being read / write in case of partial access. However a lot of
> drivers either (incorrectly) ignore partial access or mishandle error
> codes. In other c
Hi Philipp,
On 22/01/25 11:08, Philipp Stanner wrote:
drm_sched_init() has a great many parameters and upcoming new
functionality for the scheduler might add even more. Generally, the
great number of parameters reduces readability and has already caused
one missnaming in:
commit 6f1cacf4eba7 ("
Up until now we have only called the set_stall callback during
initialization when the device is off. But we will soon start calling it
to temporarily disable stall-on-fault when the device is on, so handle
that by checking if the device is on and writing SCTLR.
Signed-off-by: Connor Abbott
---
drm/msm uses the stall-on-fault model to record the GPU state on the
first GPU page fault to help debugging. On systems where the GPU is
paired with a MMU-500, there were two problems:
1. The MMU-500 doesn't de-assert its interrupt line until the fault is
resumed, which led to a storm of interr
When things go wrong, the GPU is capable of quickly generating millions
of faulting translation requests per second. When that happens, in the
stall-on-fault model each access will stall until it wins the race to
signal the fault and then the RESUME register is written. This slows
processing page f
On some SMMUv2 implementations, including MMU-500, SMMU_CBn_FSR.SS
asserts an interrupt. The only way to clear that bit is to resume the
transaction by writing SMMU_CBn_RESUME, but typically resuming the
transaction requires complex operations (copying in pages, etc.) that
can't be done in IRQ cont
On Wed, Jan 22, 2025 at 05:23:44PM +0100, Marijn Suijten wrote:
> Some SoCs such as SC7280 (used in the Fairphone 5) have only a single
> DSC "hard slice" encoder. The current hardcoded use of 2:2:1 topology
> (2 LM and 2 DSC for a single interface) make it impossible to use
> Display Stream Compr
On Wed, 22 Jan 2025 15:08:20 +0100
Philipp Stanner wrote:
> int drm_sched_init(struct drm_gpu_scheduler *sched,
> -const struct drm_sched_backend_ops *ops,
> -struct workqueue_struct *submit_wq,
> -u32 num_rqs, u32 credit_limit, unsigned int hang_l
On Wed, 22 Jan 2025 16:14:59 +
Tvrtko Ursulin wrote:
> On 22/01/2025 15:51, Boris Brezillon wrote:
> > On Wed, 22 Jan 2025 15:08:20 +0100
> > Philipp Stanner wrote:
> >
> >> --- a/drivers/gpu/drm/panthor/panthor_sched.c
> >> +++ b/drivers/gpu/drm/panthor/panthor_sched.c
> >> @@ -3272,6 +3
On 2025-01-21 16:58:24, Luca Weiss wrote:
> Hi Marijn,
>
> On Tue Jan 21, 2025 at 12:06 AM CET, Marijn Suijten wrote:
> > Some SoCs such as SC7280 (used in the FairPhone 5) have only a single
> > DSC "hard slice" encoder. The current hardcoded use of 2:2:1 topology
> > (2 LM and 2 DSC for a singl
On 22/01/2025 15:51, Boris Brezillon wrote:
On Wed, 22 Jan 2025 15:08:20 +0100
Philipp Stanner wrote:
--- a/drivers/gpu/drm/panthor/panthor_sched.c
+++ b/drivers/gpu/drm/panthor/panthor_sched.c
@@ -3272,6 +3272,7 @@ group_create_queue(struct panthor_group *group,
const str
Some SoCs such as SC7280 (used in the Fairphone 5) have only a single
DSC "hard slice" encoder. The current hardcoded use of 2:2:1 topology
(2 LM and 2 DSC for a single interface) make it impossible to use
Display Stream Compression panels with mainline, which is exactly what's
installed on the Fa
On Wed, 22 Jan 2025 15:08:20 +0100
Philipp Stanner wrote:
> --- a/drivers/gpu/drm/panthor/panthor_sched.c
> +++ b/drivers/gpu/drm/panthor/panthor_sched.c
> @@ -3272,6 +3272,7 @@ group_create_queue(struct panthor_group *group,
> const struct drm_panthor_queue_create *args)
> {
>
Am 22.01.25 um 16:23 schrieb Philipp Stanner:
On Wed, 2025-01-22 at 16:06 +0100, Christian König wrote:
Am 22.01.25 um 15:48 schrieb Philipp Stanner:
On Wed, 2025-01-22 at 15:34 +0100, Christian König wrote:
Am 22.01.25 um 15:08 schrieb Philipp Stanner:
drm_sched_init() has a great many param
On Wed, Jan 22, 2025 at 04:06:10PM +0100, Christian König wrote:
> Am 22.01.25 um 15:48 schrieb Philipp Stanner:
> > On Wed, 2025-01-22 at 15:34 +0100, Christian König wrote:
> > > Am 22.01.25 um 15:08 schrieb Philipp Stanner:
> > > > drm_sched_init() has a great many parameters and upcoming new
>
Am 22.01.25 um 15:48 schrieb Philipp Stanner:
On Wed, 2025-01-22 at 15:34 +0100, Christian König wrote:
Am 22.01.25 um 15:08 schrieb Philipp Stanner:
drm_sched_init() has a great many parameters and upcoming new
functionality for the scheduler might add even more. Generally, the
great number of
On Wed, Jan 22, 2025 at 03:48:54PM +0100, Philipp Stanner wrote:
> On Wed, 2025-01-22 at 15:34 +0100, Christian König wrote:
> > Am 22.01.25 um 15:08 schrieb Philipp Stanner:
> > > drm_sched_init() has a great many parameters and upcoming new
> > > functionality for the scheduler might add even mor
Am 22.01.25 um 15:08 schrieb Philipp Stanner:
drm_sched_init() has a great many parameters and upcoming new
functionality for the scheduler might add even more. Generally, the
great number of parameters reduces readability and has already caused
one missnaming in:
commit 6f1cacf4eba7 ("drm/nouve
On Wed, Jan 22, 2025 at 03:08:20PM +0100, Philipp Stanner wrote:
> drm_sched_init() has a great many parameters and upcoming new
> functionality for the scheduler might add even more. Generally, the
> great number of parameters reduces readability and has already caused
> one missnaming in:
>
> co
On 1/17/2025 2:46 AM, Konrad Dybcio wrote:
> On 15.01.2025 8:59 PM, Dmitry Baryshkov wrote:
>> On Thu, Jan 16, 2025 at 01:07:17AM +0530, Akhil P Oommen wrote:
>>> On 1/9/2025 7:27 PM, Konrad Dybcio wrote:
On 8.01.2025 11:42 PM, Akhil P Oommen wrote:
> Adreno X1-85 has an additional bit whi
drm_sched_init() has a great many parameters and upcoming new
functionality for the scheduler might add even more. Generally, the
great number of parameters reduces readability and has already caused
one missnaming in:
commit 6f1cacf4eba7 ("drm/nouveau: Improve variable name in
nouveau_sched_init
On 2025-01-20 3:46 pm, Connor Abbott wrote:
On some SMMUv2 implementations, including MMU-500, SMMU_CBn_FSR.SS
asserts an interrupt. The only way to clear that bit is to resume the
transaction by writing SMMU_CBn_RESUME, but typically resuming the
transaction requires complex operations (copying
On Tue, Jan 21, 2025 at 04:58:03PM -0800, Abhinav Kumar wrote:
>
>
> On 12/13/2024 2:14 PM, Dmitry Baryshkov wrote:
> > Continue migration to the MDSS-revision based checks and replace
> > DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check.
> >
> > Signed-off-by: Dmitry Baryshkov
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