On Wed, Oct 16, 2024 at 09:50:04AM +0200, Krzysztof Kozlowski wrote:
> On 15/10/2024 21:35, Akhil P Oommen wrote:
> > On Mon, Oct 14, 2024 at 09:40:13AM +0200, Krzysztof Kozlowski wrote:
> >> On Sat, Oct 12, 2024 at 01:59:30AM +0530, Akhil P Oommen wrote:
> >>> Update GPU node to include acd level
On Wed, Oct 16, 2024 at 09:53:58AM +0200, Krzysztof Kozlowski wrote:
> On 15/10/2024 21:13, Akhil P Oommen wrote:
> > On Mon, Oct 14, 2024 at 09:39:01AM +0200, Krzysztof Kozlowski wrote:
> >> On Sat, Oct 12, 2024 at 01:59:29AM +0530, Akhil P Oommen wrote:
> >>> Add a new schema which extends opp-v2
Add support for allocating the concurrent writeback mux as part of the
WB allocation
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 17 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 ++
2 files changed, 17 insertions(+), 2
Add support for RM to reserve dedicated CWB PINGPONGs and CWB muxes
For concurrent writeback, even-indexed CWB muxes must be assigned to
even-indexed LMs and odd-indexed CWB muxes for odd-indexed LMs. The same
even/odd rule applies for dedicated CWB PINGPONGs.
Track the CWB muxes in the global st
From: Dmitry Baryshkov
All resource allocation is centered around the LMs. Then other blocks
(except DSCs) are allocated basing on the LMs that was selected, and LM
powers up the CRTC rather than the encoder.
Moreover if at some point the driver supports encoder cloning,
allocating resources fro
Set writeback encoders as possible clones for DSI encoders and vice
versa.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 32 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 ++
drivers/gpu/drm/msm/disp
Add the cwb_enabled flag to msm_display topology and adjust the toplogy
to account for concurrent writeback
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 10 --
drivers/gpu/drm/msm/msm_drv.h
The CWB mux has a pending flush bit and *_active register.
Add support for configuring them within the dpu_hw_ctl layer.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 13 ++
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys
For concurrent writeback, the real time encoder is responsible for
trigger flush and trigger start. Return early for trigger start and
trigger flush for the concurrent writeback encoders.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
Add a helper that will handle the correct order of the encoder kickoffs
for concurrent writeback.
For concurrent writeback, the realtime encoder must always kickoff last
as it will call the trigger flush and start.
This avoids the following scenario where the writeback encoder
increments the pend
Starting the frame done timer before the encoder is finished kicking off
can lead to unnecessary frame done timeouts when the device is
experiencing heavy load (ex. when debug logs are enabled).
Thus, create a separate API for starting the encoder frame done timer and
call it after the encoder kic
Adjust QoS remapper, OT limit, and CDP parameters to account for
concurrent writeback
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/dr
Change pingpong index and names to distinguish between general use
pingpong blocks and pingpong blocks dedicated for concurrent writeback
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8
drivers/gpu/drm/msm/dis
From: Esha Bharadwaj
Adjust the WB_MUX configuration to account for using dedicated CWB
pingpong blocks.
Signed-off-by: Esha Bharadwaj
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletio
From: Dmitry Baryshkov
Stop poking into CRTC state from dpu_encoder.c, fill CRTC HW resources
from dpu_crtc_assign_resources().
Signed-off-by: Dmitry Baryshkov
[quic_abhin...@quicinc.com: cleaned up formatting]
Signed-off-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm
From: Dmitry Baryshkov
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to use CRTC id in preparation for the next step.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 +--
drivers/gpu/drm
The CWB mux has its own registers and set of operations. Add dpu_hw_cwb
abstraction to allow driver to configure the CWB mux.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/Makefile| 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.c | 73 +
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 75 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.
From: Esha Bharadwaj
Implement instance of snapshot function to dump new registers used
for cwb
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Esha Bharadwaj
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/driver
We cannot support both CWB and CDM simultaneously as this would require
2 CDM blocks and currently our hardware only supports 1 CDM block at
most.
Thus return an error if both CWB and CDM are enabled.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4
1 file cha
Add a common helper to check if the given CRTC state is in clone mode.
This can be used by drivers to help detect if a CRTC is being shared by
multiple encoders
Signed-off-by: Jessica Zhang
---
NOTE: The appropriate KUnit tests will be added in a separate series
---
drivers/gpu/drm/drm_crtc.c |
From: Esha Bharadwaj
Add a new block for concurrent writeback mux to the SM8650 HW catalog
Signed-off-by: Esha Bharadwaj
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 21 +
drivers/gpu/drm/msm/disp/dpu
Check that all encoders attached to a given CRTC are valid
possible_clones of each other.
Signed-off-by: Jessica Zhang
---
NOTE: Appropriate KUnit tests for this change will be posted in a
separate series
---
drivers/gpu/drm/drm_atomic_helper.c | 23 +++
1 file changed, 23 i
If the clone mode enabled status is changing, a modeset needs to happen
so that the resources can be reassigned
Signed-off-by: Jessica Zhang
---
NOTE: As noted by Sima in the v1 [1], the DPU driver doesn't handle
crtc_state->mode_changed correctly. However, fixing this is out of the
scope of thi
From: Dmitry Baryshkov
The struct dpu_rm_requirements was used to wrap display topology and
hw resources, which meant INTF indices. As of commit ef58e0ad3436
("drm/msm/dpu: get INTF blocks directly rather than through RM") the hw
resources struct was removed, leaving struct dpu_rm_requirements
co
DPU supports a single writeback session running concurrently with primary
display when the CWB mux is configured properly. This series enables
clone mode for DPU driver and adds support for programming the CWB mux
in cases where the hardware has dedicated CWB pingpong blocks. Currently,
the CWB har
On Wed, Oct 16, 2024 at 5:13 AM Antonino Maniscalco
wrote:
>
> On 10/8/24 11:10 PM, Kees Bakker wrote:
> > Op 03-10-2024 om 18:12 schreef Antonino Maniscalco:
> >> Add trace points corresponding to preemption being triggered and being
> >> completed for latency measurement purposes.
> >>
> >> Revi
Hi Dave,
A few fixes for v6.12, see description below
The following changes since commit 15302579373ed2c8ada629e9e7bcf9569393a48d:
drm/msm/dpu: enable writeback on SM6350 (2024-09-02 02:53:44 +0300)
are available in the Git repository at:
https://gitlab.freedesktop.org/drm/msm.git tags/drm
On 10/8/24 11:10 PM, Kees Bakker wrote:
Op 03-10-2024 om 18:12 schreef Antonino Maniscalco:
Add trace points corresponding to preemption being triggered and being
completed for latency measurement purposes.
Reviewed-by: Akhil P Oommen
Tested-by: Rob Clark
Tested-by: Neil Armstrong # on SM865
On 15/10/2024 20:05, Adrián Larumbe wrote:
Hi Tvrtko,
On 10.10.2024 10:50, Tvrtko Ursulin wrote:
On 09/10/2024 23:55, Adrián Larumbe wrote:
Hi Tvrtko,
On 04.10.2024 14:41, Tvrtko Ursulin wrote:
Hi Adrian,
On 03/10/2024 00:45, Adrián Larumbe wrote:
Some drivers must allocate a considera
On 15/10/2024 21:13, Akhil P Oommen wrote:
> On Mon, Oct 14, 2024 at 09:39:01AM +0200, Krzysztof Kozlowski wrote:
>> On Sat, Oct 12, 2024 at 01:59:29AM +0530, Akhil P Oommen wrote:
>>> Add a new schema which extends opp-v2 to support a new vendor specific
>>> property required for Adreno GPUs found
On 15/10/2024 21:35, Akhil P Oommen wrote:
> On Mon, Oct 14, 2024 at 09:40:13AM +0200, Krzysztof Kozlowski wrote:
>> On Sat, Oct 12, 2024 at 01:59:30AM +0530, Akhil P Oommen wrote:
>>> Update GPU node to include acd level values.
>>>
>>> Signed-off-by: Akhil P Oommen
>>> ---
>>> arch/arm64/boot/d
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