Only 2 DSC engines are allowed, or no DSC is involved currently.
We need 4 DSC in quad-pipe topology in future. So let's only configure
DSC engines in use, instread of maximum number of DSC engines.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 -
1 file
If DSC is enabled, the only case is with 2 DSC engines so far. More
usage case will be added, such as 4 DSC in 4:4:2 topoplogy.
So get real number of DSCs to decide whether DSC merge is needed.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h| 2 ++
drivers/gpu/drm/msm/dis
If DSC is enabled, the only case is with 2 DSC engines so far. And
DSC in all pipes are configured by default.
More usage case will be added, such as 4 DSC in 4:4:2 topoplogy.
Pipe number is extended in future to support quad-pipe. But only
some of 4 pipes are used in non quad-pipe. So number of D
On 10/8/2024 1:00 AM, Neil Armstrong wrote:
Hi,
On 01/10/2024 09:37, neil.armstr...@linaro.org wrote:
Hi,
On 30/09/2024 21:19, Jessica Zhang wrote:
On 9/30/2024 7:17 AM, neil.armstr...@linaro.org wrote:
On 25/09/2024 00:59, Jessica Zhang wrote:
When running igt-test on QRD8650, I
On Tue, Oct 08, 2024 at 10:00:57AM GMT, Neil Armstrong wrote:
> Hi,
>
> On 01/10/2024 09:37, neil.armstr...@linaro.org wrote:
> > Hi,
> >
> > On 30/09/2024 21:19, Jessica Zhang wrote:
> > >
> > >
> > > On 9/30/2024 7:17 AM, neil.armstr...@linaro.org wrote:
> > > > On 25/09/2024 00:59, Jessica Z
Hi,
On 01/10/2024 09:37, neil.armstr...@linaro.org wrote:
Hi,
On 30/09/2024 21:19, Jessica Zhang wrote:
On 9/30/2024 7:17 AM, neil.armstr...@linaro.org wrote:
On 25/09/2024 00:59, Jessica Zhang wrote:
When running igt-test on QRD8650, I get:
# IGT_FRAME_DUMP_PATH=$PWD FRAME_PNG_FILE_N
