From: Mahadevan
Add devicetree changes to enable MDSS0 display-subsystem its
display-controller(DPU) for Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 89 +++
1 file changed, 89 insertions(+)
diff --git a/arch/a
anged, 951 insertions(+)
---
base-commit: e390603cfa79c860ed35e073f5fe77805b067a8e
change-id: 20240930-patchv3_1-600cbc1549e8
Best regards,
--
Mahadevan
From: Mahadevan
Add Mobile Display Subsystem (MDSS) support for the SA8775P platform.
Signed-off-by: Mahadevan
---
drivers/gpu/drm/msm/msm_mdss.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index
faa88fd6eb4d
From: Mahadevan
Document the DPU for Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
.../bindings/display/msm/qcom,sa8775p-dpu.yaml | 122 +
1 file changed, 122 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml
b/D
From: Mahadevan
Add definitions for the display hardware used on the
Qualcomm SA8775P platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Mahadevan
---
.../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h| 485 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
From: Mahadevan
Document the MDSS hardware found on the Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
.../bindings/display/msm/qcom,sa8775p-mdss.yaml| 241 +
1 file changed, 241 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sa
On Thu, Sep 26, 2024 at 11:16:53PM +0200, Antonino Maniscalco wrote:
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +:orphan:
Why don't this be added to toctree in Documentation/gpu/index.rst?
> +
> +=
> +MSM Preemtion
> +=
s/Preemtion/Preemption/
> +This mechanism can be
On 9/30/2024 7:17 AM, neil.armstr...@linaro.org wrote:
On 25/09/2024 00:59, Jessica Zhang wrote:
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dis
This patch series add dpu support for MSM8996/MSM8953/MSM8937/MSM8917 SoCs.
This parch series was tested on many devices:
- Xiaomi Redmi 5A (msm8917, video panel)
- Xiaomi Redmi Note 5A (msm8917, video panel)
- Xiaomi Redmi Note 5A Prime (msm8940, video panel)
- Motorola G5S (msm8937, video panel
From: Dmitry Baryshkov
Add support for MSM8917, which has MDP5 v1.15. It looks like
trimmed down version of MSM8937. Even fewer PP, LM and no DSI1.
Signed-off-by: Dmitry Baryshkov
[Remove intr_start from CTLs config, reword the commit]
Signed-off-by: Barnabás Czémán
---
.../drm/msm/disp/dpu1/
From: Dmitry Baryshkov
Add support for MSM8937, which has MDP5 v1.14. It looks like
trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC,
etc.
Signed-off-by: Dmitry Baryshkov
[Remove intr_start from CTLs config, reword the commit]
Signed-off-by: Barnabás Czémán
---
.../drm/msm
From: Konrad Dybcio
Add support for MSM8996, which - fun fact - was the SoC that this driver
(or rather SDE, its downstream origin) was meant for and first tested on.
It has some hardware that differs from the modern SoCs, so not a lot of
current structs could have been reused. It's also seeming
From: Dmitry Baryshkov
Add support for MSM8953, which has MDP5 v1.16. It looks like
trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC,
etc.
Signed-off-by: Dmitry Baryshkov
[Remove intr_start from CTLs config, reword the commit]
Signed-off-by: Barnabás Czémán
---
.../drm/msm
On 9/26/2024 6:39 PM, Dmitry Baryshkov wrote:
On Thu, Sep 26, 2024 at 04:31:36PM GMT, Mahadevan wrote:
Add definitions for the display hardware used on the
Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
Reviewed-by: Dmitry Baryshkov
Minor nit below.
[v2]
- Reorder compatible st
On 25/09/2024 00:59, Jessica Zhang wrote:
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 83 +-
d
Add documentation about the preemption feature supported by the msm
driver.
Signed-off-by: Antonino Maniscalco
---
Documentation/gpu/msm-preemption.rst | 99
1 file changed, 99 insertions(+)
diff --git a/Documentation/gpu/msm-preemption.rst
b/Documentation/
Initialize with 4 rings to enable preemption.
For now only on a750 as other targets require testing.
Add the "preemption_enabled" module parameter to override this for other
a7xx targets.
Tested-by: Rob Clark
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8550-QRD
Some userspace changes are necessary so add a flag for userspace to
advertise support for preemption when creating the submitqueue.
When this flag is not set preemption will not be allowed in the middle
of the submitted IBs therefore mantaining compatibility with older
userspace.
The flag is reje
Add trace points corresponding to preemption being triggered and being
completed for latency measurement purposes.
Reviewed-by: Akhil P Oommen
Tested-by: Rob Clark
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8450-HDK
Sig
In mesa CP_SET_CTXSWITCH_IB is renamed to CP_SET_AMBLE and some other
names are changed to match KGSL. Import those changes.
The changes have not been merged yet in mesa but are necessary for this
series.
Tested-by: Rob Clark
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong
Use the postamble to reset perf counters when switching between rings,
except when sysprof is enabled, analogously to how they are reset
between submissions when switching pagetables.
Reviewed-by: Akhil P Oommen
Tested-by: Rob Clark
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Arms
This patch implements preemption feature for A6xx targets, this allows
the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
hardware as such supports multiple levels of preemption granularities,
ranging from coarse grained(ringbuffer level) to a more fine grained
such as draw-cal
Add a field to contain the pwup_reglist needed for preemption.
Signed-off-by: Antonino Maniscalco
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 26 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 13 +
3 file
Add missing bitfields to CONTEXT_SWITCH_CNTL in a6xx.xml.
Tested-by: Rob Clark
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8450-HDK
Signed-off-by: Antonino Maniscalco
---
drivers/gpu/drm/msm/registers/adreno/a6xx.xml |
Adds a field to `adreno_info` to store the GPU specific preempt record
size.
Reviewed-by: Akhil P Oommen
Tested-by: Rob Clark
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8450-HDK
Signed-off-by: Antonino Maniscalco
---
The bv_fence field of rbmemptrs was being used incorrectly as the BV
rptr shadow pointer in some places.
Add a bv_rptr field and change the code to use that instead.
Reviewed-by: Akhil P Oommen
Tested-by: Rob Clark
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM855
With preemption it is not enough to track the current_ctx_seqno globally
as execution might switch between rings.
This is especially problematic when current_ctx_seqno is used to
determine whether a page table switch is necessary as it might lead to
security bugs.
Track current context per ring.
This series implements preemption for A7XX targets, which allows the GPU to
switch to an higher priority ring when work is pushed to it, reducing latency
for high priority submissions.
This series enables L1 preemption with skip_save_restore which requires
the following userspace patches to functi
On 9/26/2024 6:54 PM, Bjorn Andersson wrote:
On Thu, Sep 26, 2024 at 04:31:33PM +0530, Mahadevan wrote:
Document the MDSS hardware found on the Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
[v2]
- Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry]
- Update
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