On 8/7/24 06:44, Dmitry Baryshkov wrote:> Could you please clarify, I was under
the impression that currently whole suspend/resume is broken, so it's more than
a dmesg message.
71174f362d67 specifically, or v6.9 more broadly regress in that we get "[dpu
error]connector not connected 3" and "[drm
On Tue, 06 Aug 2024 17:44:54 -0400, Richard Acayan wrote:
> This adds support for the speed-binned A615 GPU on SDM670.
>
> Changes since v1 (20240730013844.41951-6-mailingrad...@gmail.com):
> - add Acked-by tag (1/4)
> - add OPPs exclusive to some speed bins (3/4)
> - enable GMU by default (3/4)
This adds extra parameters that affect UBWC tiling that will be used by
the Mesa implementation of VK_EXT_host_image_copy.
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++
include/uapi/drm/msm_drm.h | 2 ++
2 files changed, 8 insertions(+)
diff -
According to downstream we should be setting RBBM_NC_MODE_CNTL to a
non-default value on a663 and a680, we don't support a663 and on a680
we're leaving it at the wrong (suboptimal) value. Just set it on all
GPUs. Similarly, plumb through level2_swizzling_dis which will be
necessary on a663.
ubwc_m
Update to Mesa commit 36a13d2b3b0 ("freedreno: fix a7xx perfcntr
countables").
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 1118 -
1 file changed, 1097 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/msm/registers/adreno/a
Make it match the MDSS settings for sc8180x and downstream.
Note that without the previous commit that exposes the value of
macrotile_mode to mesa, this will break mesa which expects the legacy
default value of 0. Therefore we do *not* want to backport it.
Signed-off-by: Connor Abbott
---
drive
After testing, there are more parameters that we're programming which
affect how UBWC tiles are laid out in memory and therefore affect
the Mesa implementation of VK_EXT_host_image_copy [1], which includes a
CPU implementation of tiling and detiling images. In particular we have:
1. ubwc_mode, whi
This was missed because we weren't using the a750-specific indexed regs.
Fixes: f3f8207d8aed ("drm/msm: Add devcoredump support for a750")
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/dr
This was missed thanks to the family mixup fixed in the previous commit.
Fixes: f3f8207d8aed ("drm/msm: Add devcoredump support for a750")
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drive
Unfortunately the first time around I made the mistake of not checking
the devcoredump file closely enough to make sure it had the right
contents. This makes sure we're actually using the a750 register lists
on a750.
Signed-off-by: Connor Abbott
---
Changes in v2:
- Add last commit fixing an inde
With a7xx, we need to import a new header for each new generation and
switch to a different list of registers, instead of making
backwards-compatible changes. Using the helpers inadvertently made a750
use the a740 list of registers, instead use the family directly to fix
this.
Fixes: f3f8207d8aed
On August 6, 2024 2:19:46 AM GMT+07:00, Abhinav Kumar
wrote:
>
>
>On 8/2/2024 12:47 PM, Dmitry Baryshkov wrote:
>> During suspend/resume process all connectors are explicitly disabled and
>> then reenabled. However resume fails because of the connector_status check:
>>
>> [ 1185.831970] [dpu err
On August 5, 2024 9:27:39 AM GMT+07:00, Leonard Lausen
wrote:
>Dear Dmitry,
>
>Thank you for the patch. Unfortunately, the patch triggers a regression with
>respect to DRM CRTC state handling. With the patch applied, suspending and
>resuming a lazor sc7180 with external display connected, looses
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