Re: (subset) [PATCH 0/3] Update Konrad Dybcio's email addresses

On Fri, 26 Jul 2024 13:18:22 +0200, Konrad Dybcio wrote: > Patch 3 should probably go straight to Rob's dt-bindings tree > > Applied, thanks! [1/3] mailmap: Add an entry for Konrad Dybcio commit: 72c93f3e0dcdc05fceafcb32e79352a45716d181 [2/3] MAINTAINERS: Update Konrad Dybcio's email ad

Re: [PATCH v5 02/12] drm/msm/dpu: relax YUV requirements

On Wed, 31 Jul 2024 at 22:36, Abhinav Kumar wrote: > > > > On 6/26/2024 2:45 PM, Dmitry Baryshkov wrote: > > YUV formats require only CSC to be enabled. Even decimated formats > > should not require scaler. Relax the requirement and don't check for the > > scaler block while checking if YUV format

Re: [PATCH v5 02/12] drm/msm/dpu: relax YUV requirements

On 6/26/2024 2:45 PM, Dmitry Baryshkov wrote: YUV formats require only CSC to be enabled. Even decimated formats should not require scaler. Relax the requirement and don't check for the scaler block while checking if YUV format can be enabled. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU sup

Re: [PATCH v5 01/12] drm/msm/dpu: limit QCM2290 to RGB formats only

On 6/26/2024 2:45 PM, Dmitry Baryshkov wrote: The QCM2290 doesn't have CSC blocks, so it can not support YUV formats even on ViG blocks. Fix the formats declared by _VIG_SBLK_NOSCALE(). Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS") Signed-off-by: Dmitry Baryshkov --- driver

[PATCH] drm/msm/dpu: move dpu_encoder's connector assignment to atomic_enable()

For cases where the crtc's connectors_changed was set without enable/active getting toggled , there is an atomic_enable() call followed by an atomic_disable() but without an atomic_mode_set(). This results in a NULL ptr access for the dpu_encoder_get_drm_fmt() call in the atomic_enable() as the dp

[PATCH v2 2/2] arm64: dts: qcom: sc7280: Add 0x81 Adreno speed bin

From: Eugene Lepshy A642L (speedbin 0x81) uses index 4, so this commit sets the fourth bit for A642L supported opps. Signed-off-by: Eugene Lepshy Signed-off-by: Danila Tikhonov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 1 file changed, 4 insertions(+),

[PATCH v2 1/2] drm/msm/a6xx: Add A642L speedbin (0x81)

From: Eugene Lepshy According to downstream, A642L's speedbin is 129 and uses 4 as index Signed-off-by: Eugene Lepshy Signed-off-by: Danila Tikhonov Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/ms

[PATCH v2 0/2] Add Qualcomm Adreno 642L speedbin and update SC7280 OPPs

This patch series adds support for the A642L GPU speedbin (0x81) to the Adreno driver and updates the device tree for the SC7280 platform to include this new speedbin. The A642L is used in the Qualcomm Snapdragon SM7325 SoCs family, which is identical to the SC7280, just as the SM7125 is identical

Re: [PATCH v2 0/3] drm/msm: Further expose UBWC tiling parameters

On Wed, Jul 3, 2024 at 3:54 AM Connor Abbott wrote: > > After testing, there are more parameters that we're programming which > affect how UBWC tiles are laid out in memory and therefore affect > the Mesa implementation of VK_EXT_host_image_copy [1], which includes a > CPU implementation of tiling

Re: [PATCH 0/4] drm/msm/adreno: Add A615 GPU for SDM670 and Pixel 3a

On Mon, 29 Jul 2024 21:38:45 -0400, Richard Acayan wrote: > This adds support for the speed-binned A615 GPU on SDM670. > > Richard Acayan (4): > dt-bindings: display/msm/gmu: Add SDM670 compatible > drm/msm/adreno: add a615 support > arm64: dts: qcom: sdm670: add gpu > arm64: dts: qcom:

Re: [PATCH 3/4] arm64: dts: qcom: sdm670: add gpu

On Mon, Jul 29, 2024 at 09:38:48PM GMT, Richard Acayan wrote: > The Snapdragon 670 has the Adreno A615 GPU. Add it along with its device > tree dependencies. > > Signed-off-by: Richard Acayan > --- > arch/arm64/boot/dts/qcom/sdm670.dtsi | 168 +++ > 1 file changed, 168 in