On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
Commit e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths") changed
the block length from a wrong value to another wrong value.
Use the correct one this time.
No that change is correct as well.
After we moved to sub-blk parsing, we have enc an
On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
DPU_DSC_OUTPUT_CTRL should be enabled for all platforms with a CTL
CFG 1.0.0. SC7280 is one of them. Add it.
sc7280 and all other chipsets using DSC 1.2 use dpu_hw_dsc_init_1_2 and
not dpu_hw_dsc_init.
dpu_hw_dsc_init_1_2 assigns the dsc_bind_pi
On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
Commit 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2
macros") unrolled a macro incorrectly. Fix that.
No, its correct from what i can tell.
Before inlining it was using PP_BLK_DITHER macro and not PP_BLK.
PP_BLK_DITHER has a len of 0
On 9/15/2023 6:07 PM, Dmitry Baryshkov wrote:
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
Currently DP driver is executed independent of PM runtime framework.
This lead DP driver incompatible with others. Incorporating pm runtime
Why is it incompatible? Which others are mentioned here
Commit 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2
macros") unrolled a macro incorrectly. Fix that.
Fixes: 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 8
1 fi
Commit e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths") changed
the block length from a wrong value to another wrong value.
Use the correct one this time.
Fixes: e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/disp/dpu1/catalog
DPU_DSC_OUTPUT_CTRL should be enabled for all platforms with a CTL
CFG 1.0.0. SC7280 is one of them. Add it.
Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
1 file cha
/dpu_7_2_sc7280.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
---
base-commit: 926f75c8a5ab70567eb4c2d82fbc96963313e564
change-id: 20230920-topic-7280_dpu-59a29cedca6e
Best regards,
--
Konrad Dybcio
On 9/5/2023 10:43 AM, Dmitry Baryshkov wrote:
According to the vendor DT files, msm8998 has highest-bank-bit equal to
2. Update the data accordingly.
Fixes: 6f410b246209 ("drm/msm/mdss: populate missing data")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 2 +-
1 fi
While making the changes in [1], it was noted that the documentation
of the enable_hpd() and disable_hpd() does not make it clear that
these ops should not try to do hpd state maintenance and should only
attempt to enable/disable hpd related hardware for the connector.
The state management of thes
On 9/19/2023 2:50 AM, Dmitry Baryshkov wrote:
On Mon, 18 Sept 2023 at 20:48, Kuogee Hsieh wrote:
On 9/15/2023 6:21 PM, Dmitry Baryshkov wrote:
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
Add pm_runtime_force_suspend()/resume() to complete incorporating pm
runtime framework into DP
On 9/19/2023 2:45 AM, Dmitry Baryshkov wrote:
On Mon, 18 Sept 2023 at 23:16, Kuogee Hsieh wrote:
On 9/15/2023 5:41 PM, Dmitry Baryshkov wrote:
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
Currently DP driver use drm_helper_hpd_irq_event(), bypassing drm bridge
framework, to report H
On 20/09/2023 00:34, Adrián Larumbe wrote:
Some BO's might be mapped onto physical memory chunkwise and on demand,
like Panfrost's tiler heap. In this case, even though the
drm_gem_shmem_object page array might already be allocated, only a very
small fraction of the BO is currently backed by sy
On 20/09/2023 00:34, Adrián Larumbe wrote:
The drm-stats fdinfo tags made available to user space are drm-engine,
drm-cycles, drm-max-freq and drm-curfreq, one per job slot.
This deviates from standard practice in other DRM drivers, where a single
set of key:value pairs is provided for the who
On 20/09/2023 00:34, Adrián Larumbe wrote:
The current implementation will try to pick the highest available size
display unit as soon as the BO size exceeds that of the previous
multiplier. That can lead to loss of precision in contexts of low memory
usage.
The new selection criteria try to p
5.4-stable review patch. If anyone has any objections, please let me know.
--
From: Daniel Vetter
[ Upstream commit fd0ad3b2365c1c58aa5a761c18efc4817193beb6 ]
Apparently no one noticed that mdp5 plane states leak like a sieve
ever since we introduced plane_state->commit refcou
4.19-stable review patch. If anyone has any objections, please let me know.
--
From: Daniel Vetter
[ Upstream commit fd0ad3b2365c1c58aa5a761c18efc4817193beb6 ]
Apparently no one noticed that mdp5 plane states leak like a sieve
ever since we introduced plane_state->commit refco
On Wed, 20 Sept 2023 at 05:08, Bjorn Andersson wrote:
>
> On Thu, Aug 17, 2023 at 05:59:37PM +0300, Dmitry Baryshkov wrote:
> > Declare the displayport controller present on the Qualcomm SM8250 SoC.
> >
> > Signed-off-by: Dmitry Baryshkov
> > ---
> > arch/arm64/boot/dts/qcom/sm8250.dtsi | 89 +++
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