From: Rob Clark
Split out pin_count incrementing and lru updating into a separate loop
so we can take the lru lock only once for all objs. Since we are still
holding the obj lock, it is safe to split this up.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c| 45 +
From: Rob Clark
This was not strictly necessary, as page unpinning (ie. shrinker) only
cares about the resv. It did give us some extra sanity checking for
userspace controlled iova, and was useful to catch issues on kernel and
userspace side when enabling userspace iova. But if userspace screws
From: Rob Clark
Basically everywhere wants the base ptr type. So store that instead of
msm_gem_object.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 ++--
drivers/gpu/drm/msm/msm_gem.h | 2 +-
drivers/gpu/drm/msm/msm_gem_submit.c | 42 +-
From: Rob Clark
Rather than acquiring it and dropping it for each individual obj.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c| 3 ---
drivers/gpu/drm/msm/msm_ringbuffer.c | 5 +
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_ge
From: Rob Clark
I recently wrote myself a submitoverhead igt test[1] and spent a bit of
time profiling. The end result ranges from 1.6x faster for
NO_IMPLICIT_SYNC commits with 100 BOs to 2.5x faster for 1000 BOs.
[1] https://patchwork.freedesktop.org/series/121909/
Rob Clark (4):
drm/msm: T
From: Rob Clark
Mesa stopped using these pretty early in a6xx bringup. Take advantage
of this to disallow some legacy UABI.
Signed-off-by: Rob Clark
---
So, it was late 2018 when mesa stopped using relocs. At that point a6xx
support was still in a pretty early state. I guess you _could_ use
On 8/2/2023 12:46 PM, Marijn Suijten wrote:
On 2023-08-02 21:36:55, Dmitry Baryshkov wrote:
Both struct dpu_dsc_sub_blks instances declare enc subblock length to be
0x100, while the actual length is 0x9c (last register having offset 0x98).
Reduce subblock length to remove the empty register s
On 2023-08-02 21:36:54, Dmitry Baryshkov wrote:
> All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
> This includes the common block itself, enc subblocks and some empty
> space around. Change that to pass 0x4 instead, the length of common
> register block itself.
>
> Fixes:
On 2023-08-02 21:36:55, Dmitry Baryshkov wrote:
> Both struct dpu_dsc_sub_blks instances declare enc subblock length to be
> 0x100, while the actual length is 0x9c (last register having offset 0x98).
> Reduce subblock length to remove the empty register space from being
> dumped.
>
> Fixes: 0d1b10
On 2023-08-02 11:08:49, Jessica Zhang wrote:
> DPU supports a data-bus widen mode for DSI INTF.
>
> Enable this mode for all supported chipsets if widebus is enabled for DSI.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ---
> driver
I find this title very undescriptive, it doesn't really explain from/to
where this move is happening nor why.
On 2023-08-02 11:08:48, Jessica Zhang wrote:
> Move the setting of dpu_enc.wide_bus_en to
> dpu_encoder_virt_atomic_enable() so that it mirrors the setting of
> dpu_enc.dsc.
mirroring "th
On 8/2/23 19:49, Abhinav Kumar wrote:
Hi Marek
On 8/2/2023 10:25 AM, Marek Vasut wrote:
On 8/2/23 15:08, neil.armstr...@linaro.org wrote:
Hi Marek,
On 02/08/2023 14:25, Marek Vasut wrote:
On 8/2/23 10:39, neil.armstr...@linaro.org wrote:
Hi Marek,
Hi,
On 13/07/2023 20:28, Marek Vasut wr
On Wed, 2 Aug 2023 at 21:36, Dmitry Baryshkov
wrote:
>
> All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
> This includes the common block itself, enc subblocks and some empty
> space around. Change that to pass 0x4 instead, the length of common
> register block itself.
>
>
Both struct dpu_dsc_sub_blks instances declare enc subblock length to be
0x100, while the actual length is 0x9c (last register having offset 0x98).
Reduce subblock length to remove the empty register space from being
dumped.
Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chi
All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
This includes the common block itself, enc subblocks and some empty
space around. Change that to pass 0x4 instead, the length of common
register block itself.
Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relev
On Wed, 2 Aug 2023 at 21:09, Jessica Zhang wrote:
>
> Add a DATABUS_WIDEN bit to the MDP_CTRL2 register to allow DSI to enable
> databus widen mode.
Reviewed-by: Dmitry Baryshkov
(The patch will probably be replaced by Rob syncing up msm headers).
>
> Signed-off-by: Jessica Zhang
> ---
> dri
On Wed, 2 Aug 2023 at 21:09, Jessica Zhang wrote:
>
> DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
> 48 bits of compressed data instead of 24.
>
> Enable this mode whenever DSC is enabled for supported chipsets.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/ms
On Wed, 2 Aug 2023 at 21:09, Jessica Zhang wrote:
>
> Move the setting of dpu_enc.wide_bus_en to
> dpu_encoder_virt_atomic_enable() so that it mirrors the setting of
> dpu_enc.dsc.
because ... ?
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 +++--
On Wed, 2 Aug 2023 at 21:09, Jessica Zhang wrote:
>
> DPU supports a data-bus widen mode for DSI INTF.
>
> Enable this mode for all supported chipsets if widebus is enabled for DSI.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ---
>
Add a DATABUS_WIDEN bit to the MDP_CTRL2 register to allow DSI to enable
databus widen mode.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index a4a1546
Move the setting of dpu_enc.wide_bus_en to
dpu_encoder_virt_atomic_enable() so that it mirrors the setting of
dpu_enc.dsc.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/
DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
48 bits of compressed data instead of 24.
Enable this mode whenever DSC is enabled for supported chipsets.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi.c | 5 +
drivers/gpu/drm/msm/dsi/dsi.h |
DSI 6G v2.5.x+ and DPU support a data-bus widen mode that allows DSI
to send 48 bits of compressed data per pclk instead of 24.
For all chipsets that support this mode, enable it whenever DSC is
enabled as recommended by the hardware programming guide.
Only enable this for command mode as we are
DPU supports a data-bus widen mode for DSI INTF.
Enable this mode for all supported chipsets if widebus is enabled for DSI.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 +++-
dri
Hi Marek
On 8/2/2023 10:25 AM, Marek Vasut wrote:
On 8/2/23 15:08, neil.armstr...@linaro.org wrote:
Hi Marek,
On 02/08/2023 14:25, Marek Vasut wrote:
On 8/2/23 10:39, neil.armstr...@linaro.org wrote:
Hi Marek,
Hi,
On 13/07/2023 20:28, Marek Vasut wrote:
MIPI_DSI_MODE_VIDEO_NO_HFP me
On 8/2/23 15:08, neil.armstr...@linaro.org wrote:
Hi Marek,
On 02/08/2023 14:25, Marek Vasut wrote:
On 8/2/23 10:39, neil.armstr...@linaro.org wrote:
Hi Marek,
Hi,
On 13/07/2023 20:28, Marek Vasut wrote:
MIPI_DSI_MODE_VIDEO_NO_HFP means the HBP period is just skipped by
DSIM.
Maybe
Drop vsync_event and vsync_event_work handlers as they are unnecessary.
In addition drop the dpu_enc_ktime_template event class as it will be
unused after the vsync_event handlers are dropped.
Signed-off-by: Jessica Zhang
---
Changes in v2:
- Dropped dpu_enc_early_kickoff event and dpu_enc_ktime_
On Wed, 02 Aug 2023 09:48:53 -0400, Jonathan Marek wrote:
> sm8550 has 16 vbif clients.
>
> This fixes the extra 2 clients (DMA4/DMA5) not having their memtype
> initialized. This fixes DMA4/DMA5 planes not displaying correctly.
>
>
Applied, thanks!
[1/1] drm/msm/dpu: increase memtype count
On 02/08/2023 15:48, Jonathan Marek wrote:
sm8550 has 16 vbif clients.
This fixes the extra 2 clients (DMA4/DMA5) not having their memtype
initialized. This fixes DMA4/DMA5 planes not displaying correctly.
Fixes: efcd0107 ("drm/msm/dpu: add support for SM8550")
Signed-off-by: Jonathan Marek
--
On Wed, 2 Aug 2023 at 16:51, Jonathan Marek wrote:
>
> sm8550 has 16 vbif clients.
>
> This fixes the extra 2 clients (DMA4/DMA5) not having their memtype
> initialized. This fixes DMA4/DMA5 planes not displaying correctly.
>
> Fixes: efcd0107 ("drm/msm/dpu: add support for SM8550")
> Signed-off-b
sm8550 has 16 vbif clients.
This fixes the extra 2 clients (DMA4/DMA5) not having their memtype
initialized. This fixes DMA4/DMA5 planes not displaying correctly.
Fixes: efcd0107 ("drm/msm/dpu: add support for SM8550")
Signed-off-by: Jonathan Marek
---
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
Hi Marek,
On 02/08/2023 14:25, Marek Vasut wrote:
On 8/2/23 10:39, neil.armstr...@linaro.org wrote:
Hi Marek,
Hi,
On 13/07/2023 20:28, Marek Vasut wrote:
MIPI_DSI_MODE_VIDEO_NO_HFP means the HBP period is just skipped by DSIM.
Maybe there is a need for new set of flags which different
On 8/2/23 10:39, neil.armstr...@linaro.org wrote:
Hi Marek,
Hi,
On 13/07/2023 20:28, Marek Vasut wrote:
MIPI_DSI_MODE_VIDEO_NO_HFP means the HBP period is just skipped by
DSIM.
Maybe there is a need for new set of flags which differentiate
between HBP skipped (i.e. NO HBP) and HBP LP
In order to simplify IRQ declarations, shift IRQ indices by 1. This
makes 0 the 'no IRQ' value. Thanks to this change, we do no longer have
to explicitly set the 'no interrupt' fields in catalog structures.
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalo
In preparation to reworking IRQ indcies, stop using raw indices in
kernel traces. Instead use a pair of register index and bit. This
corresponds closer to the values in HW catalog.
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6
In preparation to reworking IRQ indcies, stop using raw IRQ indices in
kernel output (both printk and debugfs). Instead use a pair of register
index and bit. This corresponds closer to the values in HW catalog.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2
In preparation to reworking IRQ indices, move irq_tbl access to
a separate helper.
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 48 +--
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 12 +++--
2 files changed, 4
In preparation to reworking IRQ indices, move irq_idx validation to
a separate helper.
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 22 +--
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/
The size of the irq table is static, it has MDP_INTR_MAX * 32 interrupt
entries. Provide the fixed length and drop struct_size() statement.
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 26 ---
.../gpu/drm/msm/dis
There is no point in passing the IRQ index to IRQ callbacks, no function
uses that. Drop it at last.
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
drivers/gpu/
Since commit 1e7ac595fa46 ("drm/msm/dpu: pass irq to
dpu_encoder_helper_wait_for_irq()") the
dpu_encoder_phys_wb_wait_for_commit_done expects the IRQ index rather
than the IRQ index in phys_enc->intr table, however writeback got the
older invocation in place. This was unnoticed for several releases
Having an explicit init of interrupt fields to -1 for not existing IRQs
makes it easier to forget and/or miss such initialisation, resulting in
a wrong interrupt definition.
Instead shift all IRQ indices to turn '0' to be the non-existing IRQ.
Dependencies: [1]
[1] https://patchwork.freedesktop.
On Thu, 27 Jul 2023 11:24:07 +, Ruan Jinjie wrote:
> There is no need to call the DRM_DEV_ERROR() function directly to print
> a custom message when handling an error from platform_get_irq() function
> as it is going to display an appropriate error message
> in case of a failure.
>
>
Appli
On Sun, 30 Jul 2023 04:00:52 +0300, Dmitry Baryshkov wrote:
> Apply several cleanups to the DPU's core_perf module.
>
> Changes since v4:
> - Dropped the 'extract bandwidth aggregation function' (Abhinav)
> - Fixed commit message for the patch 9 (Abhinav)
>
> Changes since v3:
> - Dropped avg_b
On Sat, 29 Jul 2023 00:33:13 +0300, Dmitry Baryshkov wrote:
> Both DPU and MDSS programming requires knowledge of some of UBWC
> parameters. This results in duplication of UBWC data between MDSS and
> DPU drivers. To remove such duplication and make the driver more
> error-prone, export respectiv
On Thu, 27 Jul 2023 17:45:38 +0300, Dmitry Baryshkov wrote:
> Please exuse me for the spam, I missed the triggered WARN_ON because of
> the dropped patch.
>
> Declaring the mask of supported interrupts proved to be error-prone. It
> is very easy to add a bit with no corresponding backing block o
On Wed, 26 Jul 2023 18:57:18 +0530, Amit Pundir wrote:
> Add and document the reserved memory region property in the
> mdss-common schema.
>
> For now (sdm845-db845c), it points to a framebuffer memory
> region reserved by the bootloader for splash screen.
>
>
> [...]
Applied, thanks!
[1/2]
On 27/07/2023 14:24, Ruan Jinjie wrote:
There is no need to call the DRM_DEV_ERROR() function directly to print
a custom message when handling an error from platform_get_irq() function
as it is going to display an appropriate error message
in case of a failure.
Signed-off-by: Ruan Jinjie
---
On Wed, 2 Aug 2023 at 11:15, Neil Armstrong wrote:
>
> Hi,
>
> On 02/08/2023 03:18, Dmitry Baryshkov wrote:
> > Define a helper for creating simple transparent bridges which serve the
> > only purpose of linking devices into the bridge chain up to the last
> > bridge representing the connector. Th
Hi Marek,
On 13/07/2023 20:28, Marek Vasut wrote:
MIPI_DSI_MODE_VIDEO_NO_HFP means the HBP period is just skipped by DSIM.
Maybe there is a need for new set of flags which differentiate between HBP
skipped (i.e. NO HBP) and HBP LP11 ?
No, the section of the MIPI DSI spec I posted below
Hi,
On 02/08/2023 03:18, Dmitry Baryshkov wrote:
Define a helper for creating simple transparent bridges which serve the
only purpose of linking devices into the bridge chain up to the last
bridge representing the connector. This is especially useful for
DP/USB-C bridge chains, which can span ac
On 02/08/2023 10:08, Neil Armstrong wrote:
Hi Dmitry,
On 02/08/2023 03:18, Dmitry Baryshkov wrote:
Define a helper for creating simple transparent bridges which serve the
only purpose of linking devices into the bridge chain up to the last
bridge representing the connector. This is especially u
Hi Dmitry,
On 02/08/2023 03:18, Dmitry Baryshkov wrote:
Define a helper for creating simple transparent bridges which serve the
only purpose of linking devices into the bridge chain up to the last
bridge representing the connector. This is especially useful for
DP/USB-C bridge chains, which can
On 01/08/2023 22:46, Dmitry Baryshkov wrote:
On 01/08/2023 23:43, Paloma Arellano wrote:
On 8/1/2023 1:26 AM, neil.armstr...@linaro.org wrote:
On 28/07/2023 23:44, Jessica Zhang wrote:
On 7/28/2023 2:37 AM, Dmitry Baryshkov wrote:
On Fri, 28 Jul 2023 at 04:26, Paloma Arellano wrote:
Ena
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