Add displayport altmode declaration to the Type-C controller node to
enable DP altmode negotiation.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
b/arch/arm64/boot/
Enable the onboard displayport controller, connect it to QMP PHY.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
i
Add the nb7vpq904m, onboard USB-C redriver / retimer.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 52 +++-
1 file changed, 50 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
b/arch/arm64/boot/dts/qcom/qr
Declare the displayport controller present on the Qualcomm SM8250 SoC.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 93
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm825
Implement DisplayPort support for the Qualcomm RB5 platform.
Note: while testing this, I had link training issues with several
dongles with DP connectors. Other DisplayPort-USB-C dongles (with HDMI
or VGA connectors) work perfectly.
Dependencies: [1]
Soft-dependencies: [2], [3]
[1]
https://lore
It looks like DP controlled on SM8250 is the same as DP controller on
SM8350. Use the SM8350 compatible as fallback for SM8250.
Signed-off-by: Dmitry Baryshkov
---
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/d
Implement the oob_hotplug_event() callback. Translate it to the HPD
notification sent to the HPD bridge in the chain.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/drm_bridge_connector.c | 29 +++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers
In some cases the bridge drivers would like to receive hotplug events
even in the case new status is equal to the old status. In the DP case
this is used to deliver "attention" messages to the DP host. Stop
filtering the events in the drm_bridge_connector_hpd_cb() and let
drivers decide whether the
Note, this is sent as v5, since there were several revisions for this
patchset under a different series title ([1]).
USB altmodes code would send OOB notifications to the drm_connector
specified in the device tree. However as the MSM DP driver uses
drm_bridge_connector, there is no way to receive
From: Bjorn Andersson
In some implementations, such as the Qualcomm platforms, the display
driver has no way to query the current HPD state and as such it's
impossible to distinguish between disconnect and attention events.
Add a parameter to drm_connector_oob_hotplug_event() to pass the HPD
sta
On Fri, Jul 07, 2023 at 04:52:22PM -0700, Kuogee Hsieh wrote:
> In preparation of moving edp of_dp_aux_populate_bus() to
> dp_display_probe(), move dp_display_request_irq(),
> dp->parser->parse() and dp_power_client_init() to dp_display_probe()
> too.
>
> Signed-off-by: Kuogee Hsieh
> ---
> driv
On Fri, Jul 07, 2023 at 04:52:20PM -0700, Kuogee Hsieh wrote:
> Incorporating pm runtime framework into DP driver so that power
> and clock resource handling can be centralized allowing easier
> control of these resources in preparation of registering aux bus
> uring probe.
>
> Signed-off-by: Kuog
On Fri, Jul 07, 2023 at 04:52:19PM -0700, Kuogee Hsieh wrote:
> Since both pm_runtime_resume() and pm_runtime_suspend() are not
> populated at dp_pm_ops. Those pm_runtime_get/put() functions within
> dp_power.c will not have any effects in addition to increase/decrease
> power counter. Also pm_runt
On 7/7/2023 1:47 AM, Neil Armstrong wrote:
On 07/07/2023 09:18, Neil Armstrong wrote:
Hi,
On 06/07/2023 11:20, Amit Pundir wrote:
On Wed, 5 Jul 2023 at 11:09, Dmitry Baryshkov
wrote:
[Adding freedreno@ to cc list]
On Wed, 5 Jul 2023 at 08:31, Jagan Teki
wrote:
Hi Amit,
On Wed, Jul
On 7/8/2023 6:00 AM, Dmitry Baryshkov wrote:
All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
This includes the common block itself, enc subblocks and some empty
space around. Change that to pass 0x4 instead, the length of common
register block itself.
Fixes: 0d1b10c63
On 7/8/23 21:40, Dmitry Baryshkov wrote:
On Sat, 8 Jul 2023 at 22:39, Marek Vasut wrote:
On 7/8/23 17:53, Dmitry Baryshkov wrote:
On 08/07/2023 18:40, Marek Vasut wrote:
On 7/7/23 10:47, Neil Armstrong wrote:
On 07/07/2023 09:18, Neil Armstrong wrote:
Hi,
On 06/07/2023 11:20, Amit Pundir
On Sat, 8 Jul 2023 at 22:39, Marek Vasut wrote:
>
> On 7/8/23 17:53, Dmitry Baryshkov wrote:
> > On 08/07/2023 18:40, Marek Vasut wrote:
> >> On 7/7/23 10:47, Neil Armstrong wrote:
> >>> On 07/07/2023 09:18, Neil Armstrong wrote:
> Hi,
>
> On 06/07/2023 11:20, Amit Pundir wrote:
> >
On 7/8/23 17:53, Dmitry Baryshkov wrote:
On 08/07/2023 18:40, Marek Vasut wrote:
On 7/7/23 10:47, Neil Armstrong wrote:
On 07/07/2023 09:18, Neil Armstrong wrote:
Hi,
On 06/07/2023 11:20, Amit Pundir wrote:
On Wed, 5 Jul 2023 at 11:09, Dmitry Baryshkov
wrote:
[Adding freedreno@ to cc list
On 08/07/2023 18:40, Marek Vasut wrote:
On 7/7/23 10:47, Neil Armstrong wrote:
On 07/07/2023 09:18, Neil Armstrong wrote:
Hi,
On 06/07/2023 11:20, Amit Pundir wrote:
On Wed, 5 Jul 2023 at 11:09, Dmitry Baryshkov
wrote:
[Adding freedreno@ to cc list]
On Wed, 5 Jul 2023 at 08:31, Jagan Teki
On 7/7/23 10:47, Neil Armstrong wrote:
On 07/07/2023 09:18, Neil Armstrong wrote:
Hi,
On 06/07/2023 11:20, Amit Pundir wrote:
On Wed, 5 Jul 2023 at 11:09, Dmitry Baryshkov
wrote:
[Adding freedreno@ to cc list]
On Wed, 5 Jul 2023 at 08:31, Jagan Teki
wrote:
Hi Amit,
On Wed, Jul 5, 2023
All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
This includes the common block itself, enc subblocks and some empty
space around. Change that to pass 0x4 instead, the length of common
register block itself.
Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relev
Both struct dpu_dsc_sub_blks instances declare enc subblock length to be
0x100, while the actual length is 0x9c (last register having offset 0x98).
Reduce subblock length to remove the empty register space from being
dumped.
Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chi
On 8.07.2023 01:48, Dmitry Baryshkov wrote:
> On 08/07/2023 02:25, Konrad Dybcio wrote:
>> On 7.07.2023 22:37, Dmitry Baryshkov wrote:
>>> It was noticed that dpu_kms_hw_init()'s error path contains several
>>> labels which point to the same code path. Replace all of them with a
>>> single label.
>
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