[Adding freedreno@ to cc list]
On Wed, 5 Jul 2023 at 08:31, Jagan Teki wrote:
>
> Hi Amit,
>
> On Wed, Jul 5, 2023 at 10:15 AM Amit Pundir wrote:
> >
> > Hi Marek,
> >
> > On Wed, 5 Jul 2023 at 01:48, Marek Vasut wrote:
> > >
> > > Do not generate the HS front and back porch gaps, the HSA gap a
On 7/4/2023 10:28 AM, Dmitry Baryshkov wrote:
On Tue, 4 Jul 2023 at 19:10, Abhinav Kumar wrote:
On 7/4/2023 4:52 AM, Dmitry Baryshkov wrote:
On Tue, 4 Jul 2023 at 13:06, Dmitry Baryshkov
wrote:
On Tue, 4 Jul 2023 at 07:04, Abhinav Kumar wrote:
On 7/3/2023 7:20 PM, Dmitry Baryshko
To let the probe function bail early if any of the resources is
unavailable, move resource allocattion from kms_init directly to the
probe callback. While we are at it, replace irq_of_parse_and_map() with
platform_get_irq().
This also drops devm_iounmap() calls. It is too early to have them
_dpu_k
To let the probe function bail early if any of the resources is
unavailable, move resource allocattion from kms_init directly to the
probe callback. While we are at it, replace irq_of_parse_and_map() with
platform_get_irq().
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers
To let the probe function bail early if any of the resources is
unavailable, move resource allocattion from kms_init directly to the
probe callback.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 100 ++-
1 file chan
In preparation of moving resource allocation to the probe time, allow
MSM KMS drivers to pass struct msm_kms pointer via msm_drv_probe().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +-
drivers/gpu/drm/msm/disp
This patchset was left untouched for almost a year. Let's reiterate it
in attempt to solve the long-standing issue.
As discussed several times on IRC, move display subdriver resource
allocation from kms_init to probe time to let it bail early.
Changes since v3:
- Fixed MMIO unmaping in the DPU ca
On Tue, 4 Jul 2023 at 18:55, Abhinav Kumar wrote:
>
>
>
> On 7/4/2023 8:03 AM, Dmitry Baryshkov wrote:
> > Move perf mode handling for the bandwidth to
> > _dpu_core_perf_crtc_update_bus() rather than overriding per-CRTC data
> > and then aggregating known values.
> >
> > Note, this changes the fi
On Tue, 4 Jul 2023 at 19:10, Abhinav Kumar wrote:
>
>
>
> On 7/4/2023 4:52 AM, Dmitry Baryshkov wrote:
> > On Tue, 4 Jul 2023 at 13:06, Dmitry Baryshkov
> > wrote:
> >>
> >> On Tue, 4 Jul 2023 at 07:04, Abhinav Kumar
> >> wrote:
> >>>
> >>>
> >>>
> >>> On 7/3/2023 7:20 PM, Dmitry Baryshkov wrot
On Tue, 4 Jul 2023 at 19:36, Rob Clark wrote:
>
> From: Rob Clark
>
> Recently, a WARN_ON() was introduced to ensure that revn is filled before
> adreno_is_aXYZ is called. This however doesn't work very well when revn is
> 0 by design (such as for A635).
>
> Cc: Konrad Dybcio
> Fixes: cc943f43ec
From: Rob Clark
Recently, a WARN_ON() was introduced to ensure that revn is filled before
adreno_is_aXYZ is called. This however doesn't work very well when revn is
0 by design (such as for A635).
Cc: Konrad Dybcio
Fixes: cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified before
bein
From: Rob Clark
These fields are deprecated. But any userspace new enough to support
a690 also knows how to identify the GPU based on chip-id.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 2 --
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 3 ++-
2 files changed, 2
On 7/4/2023 9:01 AM, Jonathan Marek wrote:
Note that with this, DMA4/DMA5 are still non-functional, but at least
display *something* in modetest instead of nothing or underflow.
Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550")
Signed-off-by: Jonathan Marek
---
Reviewed-by: Abhin
On 7/4/2023 4:52 AM, Dmitry Baryshkov wrote:
On Tue, 4 Jul 2023 at 13:06, Dmitry Baryshkov
wrote:
On Tue, 4 Jul 2023 at 07:04, Abhinav Kumar wrote:
On 7/3/2023 7:20 PM, Dmitry Baryshkov wrote:
On 03/07/2023 05:01, Abhinav Kumar wrote:
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
Note that with this, DMA4/DMA5 are still non-functional, but at least
display *something* in modetest instead of nothing or underflow.
Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 8 +++-
1 file cha
On 7/4/2023 8:03 AM, Dmitry Baryshkov wrote:
This function does nothing, just clears several data pointers. Drop it
now.
Now, it doesnt even do that. Just resets the clk_rate to 0.
Acked-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.
On 7/4/2023 8:03 AM, Dmitry Baryshkov wrote:
Move perf mode handling for the bandwidth to
_dpu_core_perf_crtc_update_bus() rather than overriding per-CRTC data
and then aggregating known values.
Note, this changes the fix_core_ab_vote. Previously it would be
multiplied per the CRTC number, no
On 7/4/2023 8:03 AM, Dmitry Baryshkov wrote:
Currently debugfs provides separate 'modes' to override calculated
MDP_CLK rate and interconnect bandwidth votes. Change that to allow
overriding individual values (e.g. one can override just clock or just
average bandwidth vote).
Signed-off-by: Dm
This function does nothing, just clears several data pointers. Drop it
now.
Acked-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 --
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 6 --
drivers/gpu/drm/msm/disp/dpu1/dpu_kms
Remove dpu_core_perf::dev and dpu_core_perf::debugfs_root fields, they
are not used by the code.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 6 --
drivers/gpu/drm/msm/di
dpu_core_perf should not make decisions on the maximum possible core
clock rate. Pass the value from dpu_kms_hw_init().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 11 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 8 ++--
drivers/gpu/drm
The dev_pm_opp_set_rate() already contains a call for clk_round_rate for
the passed value. Stop calling it manually from
_dpu_core_perf_get_core_clk_rate(). It is slightly incorrect to call it
this way, as we should round the final calculated clock rate rather than
rounding all the intermediate val
dpu_core_perf.c contains several multi-line conditions which are hard to
comprehent because of the indentation. Rework the identation of these
conditions to make it easier to understand them.
Reviewed-by: Abhinav Kumar
Acked-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm
Simplify dpu_core_perf code by using only dpu_perf_cfg instead of using
full-featured catalog data.
Acked-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 58 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 8 +--
drivers
The stop_req is true only in the dpu_crtc_disable() case, when
crtc->enable has already been set to false. This renders the stop_req
argument useless. Remove it completely.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 12 ++--
Currently debugfs provides separate 'modes' to override calculated
MDP_CLK rate and interconnect bandwidth votes. Change that to allow
overriding individual values (e.g. one can override just clock or just
average bandwidth vote).
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1
The values in struct dpu_core_perf_tune are fixed per the core perf
mode. Drop the 'tune' values and substitute them with known values when
performing perf management.
Note: min_bus_vote was not used at all, so it is just silently dropped.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm
Move perf mode handling for the bandwidth to
_dpu_core_perf_crtc_update_bus() rather than overriding per-CRTC data
and then aggregating known values.
Note, this changes the fix_core_ab_vote. Previously it would be
multiplied per the CRTC number, now it will be used directly for
interconnect voting
The max_per_pipe_ib is a constant across all CRTCs and is read from the
catalog. Drop corresponding calculations and read the value directly at
icc_set_bw() time.
Suggested-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 17 +
Skip bandwidth aggregation and return early if there are no interconnect
paths defined for the DPU device.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_c
In preparation to refactoring the dpu_core_perf debugfs interface,
extract the bandwidth aggregation function from
_dpu_core_perf_crtc_update_bus().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 39 +++
1 file changed, 22 insertions(+), 17 de
Apply several cleanups to the DPU's core_perf module.
Changes since v1:
- Reworked overrides for the perf parameters instead of completely
dropping them. Abhinav described why these overrides are useful.
- Moved max clock rate determination to dpu_kms.c
Dmitry Baryshkov (14):
drm/msm/dpu: dro
Drop the leftover of bus-client -> interconnect conversion, the enum
dpu_core_perf_data_bus_id.
Fixes: cb88482e2570 ("drm/msm/dpu: clean up references of DPU custom bus
scaling")
Reviewed-by: Konrad Dybcio
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp
On Sun, 2 Jul 2023 at 20:24, Krzysztof Kozlowski
wrote:
>
> The DTS code coding style expects spaces around '=' sign.
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> Rob,
>
> Maybe this could go via your tree? Rebased on your for-next:
> v6.4-rc2-45-gf0ac35049606
> ---
> .../bindings/arm/arm,
On Tue, 4 Jul 2023 at 03:19, Abhinav Kumar wrote:
>
>
>
> On 7/3/2023 3:59 PM, Dmitry Baryshkov wrote:
> > On Tue, 4 Jul 2023 at 01:57, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 6/19/2023 5:08 PM, Dmitry Baryshkov wrote:
> >>> This function does nothing, just clears several data pointers.
On Sun, 2 Jul 2023 at 21:23, Krzysztof Kozlowski
wrote:
>
> The DTS code coding style expects spaces around '=' sign.
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> Rob,
>
> Maybe this could go via your tree? Rebased on your for-next:
> v6.4-rc2-45-gf0ac35049606
> ---
> .../bindings/arm/arm,
On 02/07/2023 20:23, Krzysztof Kozlowski wrote:
The DTS code coding style expects spaces around '=' sign.
Signed-off-by: Krzysztof Kozlowski
---
Rob,
Maybe this could go via your tree? Rebased on your for-next:
v6.4-rc2-45-gf0ac35049606
---
[...]
.../bindings/net/mediatek-dwmac.yaml
On Tue, 4 Jul 2023 at 13:06, Dmitry Baryshkov
wrote:
>
> On Tue, 4 Jul 2023 at 07:04, Abhinav Kumar wrote:
> >
> >
> >
> > On 7/3/2023 7:20 PM, Dmitry Baryshkov wrote:
> > > On 03/07/2023 05:01, Abhinav Kumar wrote:
> > >>
> > >>
> > >> On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> > >>> There
On 02-07-23, 20:23, Krzysztof Kozlowski wrote:
> The DTS code coding style expects spaces around '=' sign.
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> Rob,
>
> Maybe this could go via your tree? Rebased on your for-next:
> v6.4-rc2-45-gf0ac35049606
> ---
> .../bindings/arm/arm,coresigh
On Tue, 4 Jul 2023 at 07:04, Abhinav Kumar wrote:
>
>
>
> On 7/3/2023 7:20 PM, Dmitry Baryshkov wrote:
> > On 03/07/2023 05:01, Abhinav Kumar wrote:
> >>
> >>
> >> On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> >>> There is always a single MDP TOP block. Drop the mdp_count field and
> >>> stop de
On 28/06/2023 22:35, Konrad Dybcio wrote:
> Allow A7xx SKUs, such as the A730 GPU found on SM8450 and friends.
> They use GMU for all things DVFS, just like most A6xx GPUs.
>
> Signed-off-by: Konrad Dybcio
> ---
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 28/06/2023 22:35, Konrad Dybcio wrote:
> When booting the GMU, the QMP mailbox should be pinged about some tunables
> (e.g. adaptive clock distribution state). To achieve that, a reference to
> it is necessary. Allow it and require it with A730.
>
> Signed-off-by: Konrad Dybcio
> ---
> Docume
On 28/06/2023 22:35, Konrad Dybcio wrote:
> The GMU on the A7xx series is pretty much the same as on the A6xx parts.
> It's now "smarter", needs a bit less register writes and controls more
> things (like inter-frame power collapse) mostly internally (instead of
> us having to write to G[PM]U_[CG]X
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