Hi Dave,
A few late fixes for v6.4.. meant to send this out last week but got
distracted setting my new x13s.
The following changes since commit 5c054db54c43a5fcb5cc81012361f5e3fac37637:
drm/msm: Be more shouty if per-process pgtables aren't working
(2023-05-17 08:53:47 -0700)
are available i
On 2023-06-04 06:13:08, Dmitry Baryshkov wrote:
> Currently the driver passes the PINGPONG index to
> dpu_hw_wb_ops::bind_pingpong_blk() callback and uses separate boolean
> flag to tell whether WB should be bound or unbound. Simplify this by
> passing PINGPONG_NONE in case of unbinding and drop th
On 2023-06-04 06:13:07, Dmitry Baryshkov wrote:
> Currently the driver passes the PINGPONG index to
> dpu_hw_intf_ops::bind_pingpong_blk() callback and uses separate boolean
> flag to tell whether INTF should be bound or unbound. Simplify this by
> passing PINGPONG_NONE in case of unbinding and dro
On 2023-05-30 23:14:19, Dmitry Baryshkov wrote:
> On Tue, 30 May 2023 at 20:37, Abhinav Kumar wrote:
> >
> >
> >
> > On 5/29/2023 2:36 PM, Marijn Suijten wrote:
> > > On 2023-05-24 12:18:09, Abhinav Kumar wrote:
> > >>
> > >>
> > >> On 5/24/2023 2:48 AM, Marijn Suijten wrote:
> > >>> On 2023-05-23
On 2023-05-26 14:51:59, Dan Carpenter wrote:
> Static analysis tools complain about the -EINVAL error code being
> stored in an unsigned variable. Let's change this to match
> the clk_get_rate() function which is type unsigned long and returns
> zero on error.
>
> Fixes: 25fdd5933e4c ("drm/msm: A
On 2023-05-25 10:40:54, Kuogee Hsieh wrote:
> Add support for DSC 1.2 by providing the necessary hooks to program
> the DPU DSC 1.2 encoder.
>
> Changes in v3:
> -- fixed kernel test rebot report that "__iomem *off" is declared but not
>used at dpu_hw_dsc_config_1_2()
> -- unrolling thresh loo
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 14 --
.../drm/msm/disp/dp
The MERGE_3D_SM8150_MASK features mask is zero. Drop it completely.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 3
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 44 +++---
.../msm/disp/dpu1/catalo
Move BIT(DPU_PINGPONG_DSC) back to PINGPONG_SDM845_MASK, we do not have
to be that explicit anymore.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 8
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 8
drivers/gpu/drm/msm
The INTF_SDM845_MASK features mask is zero. Drop it completely.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 --
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 60 +
.../msm/disp/dpu1
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 16 +++---
.../msm/disp/dpu1/catalo
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h| 18 +++---
.../msm/disp/dpu1/ca
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 51 ++--
.../msm/disp/dpu1/catalog
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 88 +++---
.../msm/disp/dpu1/c
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 20 ---
.../msm/disp/dpu1/catal
Drop useless zero assignments to the dpu_ctl_cfg::features field.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 3 ---
2 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/ms
Drop useless zero assignments to the dpu_mdp_cfg::features field.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
drive
Shift dpu_ctl_cfg contents to correct the indentation of CTL blocks.
This is done in preparation to expanding the rest of hardware block
defines, so that all blocks have similar indentation.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 34 ++---
...
Since there is always just a single MDP_TOP instance, drop the enum
dpu_mdp and corresponding index value.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 2 +-
drivers/gpu/drm/msm/dis
Use more standard initialisation for .clk_ctrls definitions. Define a
single .clk_ctrls field and use array init inside.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 22 +
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 18 +++---
..
There is always a single MDP TOP block. Drop the mdp_count field and
stop declaring dpu_mdp_cfg instances as arrays.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 ++---
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 7 ++---
.../msm/disp/dpu1/catalog/d
Follow the DP example and define MSM_DSI_CONTROLLER_n enumeration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_drv.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index e13a8cbd61c9..ad4fad
In several catalog entries we did not use existing MSM_DP_CONTROLLER_n
constants. Fill them in. Also use freshly defined MSM_DSI_CONTROLLER_n
for DSI interfaces.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 6 +++---
drivers/gpu/drm/msm/disp/dpu1
For each LM there is at max 1 peer LM which can be driven by the same
CTL, so there no need to have a mask instead of just an ID of the peer
LM.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 2 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 4 +--
driv
Each MERGE_3D block has just two registers. Correct the block length
accordingly.
Fixes: 4369c93cf36b ("drm/msm/dpu: initial support for merge3D hardware block")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
sm6115 and qcm2290 do not have INTF_0. Drop corresponding interface
definitions.
Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
Fixes: 5ce224840b9e ("drm/msm/dpu: expand sm6115 catalog")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h |
Having a macro with 10 arguments doesn't seem like a good idea. It makes
it inherently harder to compare the actual structure values. Also this
leads to adding macros covering varieties of the block.
As it was previously discussed, inline all foo_BLK macros in order to
ease performing changes to t
On 2023-06-01 16:56:53, Marijn Suijten wrote:
> > +static const struct dpu_intf_cfg sm6375_intf[] = {
> > + INTF_BLK("intf_0", INTF_0, 0x0, 0x280, INTF_NONE, 0, 0, 0, 0, 0),
> > + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24,
> > INTF_SC7280_MASK,
>
> Did you forget
On 23/05/2023 09:46, Konrad Dybcio wrote:
> Document the SM6350 MDSS.
>
> Signed-off-by: Konrad Dybcio
> ---
> .../bindings/display/msm/qcom,sm6350-mdss.yaml | 214
> +
> 1 file changed, 214 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/display/msm
On 23/05/2023 09:46, Konrad Dybcio wrote:
> Document the SM6375 MDSS.
>
> Signed-off-by: Konrad Dybcio
> ---
> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216
> +
> 1 file changed, 216 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/display/msm
On 23/05/2023 09:46, Konrad Dybcio wrote:
> SC7180, SM6350 and SM6375 use a rather similar hw setup for DPU, with
> the main exception being that the last one requires an additional
> throttle clock.
>
> It is not well understood yet, but failing to toggle it on makes the
> display hardware stall
In order to simplify IRQ declarations, shift IRQ indices by 1. This
makes 0 the 'no IRQ' value. Thanks to this change, we do no longer have
to explicitly set the 'no interrupt' fields in catalog structures.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h| 4 +-
In preparation to reworking the IRQ indices, move irq_tbl access to
separate helper.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 48 +--
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 12 +++--
2 files changed, 41 insertions(+), 19 deletio
There is no point in passing the IRQ index to IRQ callbacks, no function
uses that. Drop it at last.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder
In preparation of slighly changing IRQ numbering, move DPU_IRQ_REG()
macro to the dpu_hw_interrupts.h header. Also split the DPU_IRQ_MASK()
macro into local DPU_IRQ_MASK() and the global DPU_IRQ_OFFSET() macros.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.
Simplify PINGPONG blocks setup: add new PP_BLK_NO_TE, which does not set
RDPTR irq index. Also make sure that DPU_PINGPONG_TE is set for all
TE-enabled PINGPONG blocks by setting it explicitly in PP_BLK.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h| 30 +
DPU 6.x only have DITHER registers in the PINGPONG blocks. Stop using
full-featured PP_BLK and use PP_BLK_DITHER instead.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 12 ++--
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 4 ++--
..
The dither-only PINGPONG blocks do not have the RDPTR interrupts. Stop
passing useless data to the macro and use it as a default.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h| 18 ++---
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h| 6 ++
.
As we are preparing towards expanding some of the macros, it would make
sense to change 'no interrupt' from -1 to 0. This would allow us to skip
the field assignment completely rather than having an explicit assignment
.intr_foo = -1.
Dmitry Baryshkov (8):
drm/msm/dpu: fix sc7280 and sc7180 PING
During IRQ conversion we have lost the PP_DONE interrupts for sc7280
platform. This was left unnoticed, because this interrupt is only used
for CMD outputs and probably no sc7[12]80 systems use DSI CMD panels.
Fixes: 667e9985ee24 ("drm/msm/dpu: replace IRQ lookup with the data in hw
catalog")
Sig
The single helper for both enable and disable cases is too complicated,
especially if we start adding more code to these helpers. Split it into
irq_enable and irq_disable cases.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 36 ---
.../gpu/drm/msm/di
The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the
INTF and WB are statically allocated to each encoder/phys_enc, drop the
atomic_mode_set callback and set the IRQs during encoder init.
For the CMD panel usecase some of IRQ indexes depend on the selected
resources. Move setti
Follow the _dpu_encoder_irq_control() change and split the
_dpu_encoder_resource_control_helper() into enable and disable parts.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 45 +
1 file changed, 29 insertions(+), 16 deletions(-)
diff --g
The dpu_encoder_phys_ops::atomic_mode_set() callback is mostly
redundant. Implementations only set the IRQ indices there. Move
statically allocated IRQs to dpu_encoder_phys_*_init() and set
dynamically allocated IRQs in the irq_enable() callback.
Dmitry Baryshkov (3):
drm/msm/dpu: split irq_cont
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